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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-none-eabi -global-isel=0 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-eabi -global-isel=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i32 @s32_test1(i64 %a) {6; CHECK-LABEL: s32_test1:7; CHECK: // %bb.0:8; CHECK-NEXT: lsr x0, x0, #489; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x010; CHECK-NEXT: ret11 %r = lshr i64 %a, 3212 %ret = trunc i64 %r to i3213 %x = lshr i32 %ret, 1614 ret i32 %x15}16 17define i32 @s32_test2(i64 %a) {18; CHECK-LABEL: s32_test2:19; CHECK: // %bb.0:20; CHECK-NEXT: ubfx x0, x0, #32, #1621; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x022; CHECK-NEXT: ret23 %r = lshr i64 %a, 1624 %ret = trunc i64 %r to i3225 %x = lshr i32 %ret, 1626 ret i32 %x27}28 29define <8 x i8> @v8s8_test1(<8 x i16> %a) {30; CHECK-LABEL: v8s8_test1:31; CHECK: // %bb.0:32; CHECK-NEXT: ushr v0.8h, v0.8h, #1233; CHECK-NEXT: xtn v0.8b, v0.8h34; CHECK-NEXT: ret35 %r = lshr <8 x i16> %a, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>36 %ret = trunc <8 x i16> %r to <8 x i8>37 %x = lshr <8 x i8> %ret, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>38 ret <8 x i8> %x39}40 41define <8 x i8> @v8s8_test2(<8 x i16> %a) {42; CHECK-SD-LABEL: v8s8_test2:43; CHECK-SD: // %bb.0:44; CHECK-SD-NEXT: ushr v0.8h, v0.8h, #845; CHECK-SD-NEXT: bic v0.8h, #24046; CHECK-SD-NEXT: xtn v0.8b, v0.8h47; CHECK-SD-NEXT: ret48;49; CHECK-GI-LABEL: v8s8_test2:50; CHECK-GI: // %bb.0:51; CHECK-GI-NEXT: movi v1.8h, #1552; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #853; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b54; CHECK-GI-NEXT: xtn v0.8b, v0.8h55; CHECK-GI-NEXT: ret56 %r = lshr <8 x i16> %a, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>57 %ret = trunc <8 x i16> %r to <8 x i8>58 %x = lshr <8 x i8> %ret, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>59 ret <8 x i8> %x60}61 62define <4 x i16> @v4s16_test1(<4 x i32> %a) {63; CHECK-LABEL: v4s16_test1:64; CHECK: // %bb.0:65; CHECK-NEXT: ushr v0.4s, v0.4s, #2466; CHECK-NEXT: xtn v0.4h, v0.4s67; CHECK-NEXT: ret68 %r = lshr <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16>69 %ret = trunc <4 x i32> %r to <4 x i16>70 %x = lshr <4 x i16> %ret, <i16 8, i16 8, i16 8, i16 8>71 ret <4 x i16> %x72}73 74define <4 x i16> @v4s16_test2(<4 x i32> %a) {75; CHECK-SD-LABEL: v4s16_test2:76; CHECK-SD: // %bb.0:77; CHECK-SD-NEXT: shrn v0.4h, v0.4s, #1678; CHECK-SD-NEXT: bic v0.4h, #255, lsl #879; CHECK-SD-NEXT: ret80;81; CHECK-GI-LABEL: v4s16_test2:82; CHECK-GI: // %bb.0:83; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff84; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #1685; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b86; CHECK-GI-NEXT: xtn v0.4h, v0.4s87; CHECK-GI-NEXT: ret88 %r = lshr <4 x i32> %a, <i32 8, i32 8, i32 8, i32 8>89 %ret = trunc <4 x i32> %r to <4 x i16>90 %x = lshr <4 x i16> %ret, <i16 8, i16 8, i16 8, i16 8>91 ret <4 x i16> %x92}93 94define <2 x i32> @v2s32_test1(<2 x i64> %a) {95; CHECK-LABEL: v2s32_test1:96; CHECK: // %bb.0:97; CHECK-NEXT: ushr v0.2d, v0.2d, #4898; CHECK-NEXT: xtn v0.2s, v0.2d99; CHECK-NEXT: ret100 %r = lshr <2 x i64> %a, <i64 32, i64 32>101 %ret = trunc <2 x i64> %r to <2 x i32>102 %x = lshr <2 x i32> %ret, <i32 16, i32 16>103 ret <2 x i32> %x104}105 106define <2 x i32> @v2s32_test2(<2 x i64> %a) {107; CHECK-SD-LABEL: v2s32_test2:108; CHECK-SD: // %bb.0:109; CHECK-SD-NEXT: movi d1, #0x00ffff0000ffff110; CHECK-SD-NEXT: shrn v0.2s, v0.2d, #32111; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b112; CHECK-SD-NEXT: ret113;114; CHECK-GI-LABEL: v2s32_test2:115; CHECK-GI: // %bb.0:116; CHECK-GI-NEXT: movi v1.2d, #0x0000000000ffff117; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #32118; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b119; CHECK-GI-NEXT: xtn v0.2s, v0.2d120; CHECK-GI-NEXT: ret121 %r = lshr <2 x i64> %a, <i64 16, i64 16>122 %ret = trunc <2 x i64> %r to <2 x i32>123 %x = lshr <2 x i32> %ret, <i32 16, i32 16>124 ret <2 x i32> %x125}126