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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=machine-combiner -o - -simplify-mir -mtriple=aarch64-unknown-linux-gnu -mattr=+fullfp16 -verify-machineinstrs %s | FileCheck %s3--- |4 ; ModuleID = 'lit.ll'5 source_filename = "lit.ll"6 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7 target triple = "aarch64-unknown-linux-gnu"8 9 define void @indexed_2s(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {10 entry:11 %shuffle = shufflevector <2 x float> %shuf, <2 x float> undef, <2 x i32> zeroinitializer12 br label %for.cond13 14 for.cond: ; preds = %for.cond, %entry15 %mul = fmul <2 x float> %mu, %shuffle16 %add = fadd <2 x float> %mul, %ad17 store <2 x float> %add, ptr %ret, align 1618 br label %for.cond19 }20 21 define void @indexed_2s_rev(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {22 entry:23 %shuffle = shufflevector <2 x float> %shuf, <2 x float> undef, <2 x i32> zeroinitializer24 br label %for.cond25 26 for.cond: ; preds = %for.cond, %entry27 %mul = fmul <2 x float> %shuffle, %mu28 %add = fadd <2 x float> %mul, %ad29 store <2 x float> %add, ptr %ret, align 1630 br label %for.cond31 }32 33 define void @indexed_2d(<2 x double> %shuf, <2 x double> %mu, <2 x double> %ad, ptr %ret) #0 {34 entry:35 %shuffle = shufflevector <2 x double> %shuf, <2 x double> undef, <2 x i32> zeroinitializer36 br label %for.cond37 38 for.cond: ; preds = %for.cond, %entry39 %mul = fmul <2 x double> %mu, %shuffle40 %add = fadd <2 x double> %mul, %ad41 store <2 x double> %add, ptr %ret, align 1642 br label %for.cond43 }44 45 define void @indexed_4s(<4 x float> %shuf, <4 x float> %mu, <4 x float> %ad, ptr %ret) #0 {46 entry:47 %shuffle = shufflevector <4 x float> %shuf, <4 x float> undef, <4 x i32> zeroinitializer48 br label %for.cond49 50 for.cond: ; preds = %for.cond, %entry51 %mul = fmul <4 x float> %mu, %shuffle52 %add = fadd <4 x float> %mul, %ad53 store <4 x float> %add, ptr %ret, align 1654 br label %for.cond55 }56 57 define void @indexed_4h(<4 x half> %shuf, <4 x half> %mu, <4 x half> %ad, ptr %ret) #0 {58 entry:59 %shuffle = shufflevector <4 x half> %shuf, <4 x half> undef, <4 x i32> zeroinitializer60 br label %for.cond61 62 for.cond:63 %mul = fmul <4 x half> %mu, %shuffle64 %add = fadd <4 x half> %mul, %ad65 store <4 x half> %add, ptr %ret, align 1666 br label %for.cond67 }68 69 define void @indexed_8h(<8 x half> %shuf, <8 x half> %mu, <8 x half> %ad, ptr %ret) #0 {70 entry:71 %shuffle = shufflevector <8 x half> %shuf, <8 x half> undef, <8 x i32> zeroinitializer72 br label %for.cond73 74 for.cond:75 %mul = fmul <8 x half> %mu, %shuffle76 %add = fadd <8 x half> %mul, %ad77 store <8 x half> %add, ptr %ret, align 1678 br label %for.cond79 }80 81 define void @kill_state(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad,82 ptr %ret, ptr %ret2, float %f) #0 {83 entry:84 %zero_elem = extractelement <2 x float> %shuf, i32 085 %ins = insertelement <2 x float> undef, float %zero_elem, i32 086 %shuffle = shufflevector <2 x float> %ins, <2 x float> undef, <2 x i32> zeroinitializer87 %ins2 = insertelement <2 x float> %ins, float %f, i32 188 store <2 x float> %ins2, ptr %ret2, align 889 br label %for.cond90 91 for.cond: ; preds = %for.cond, %entry92 %mul = fmul <2 x float> %mu, %shuffle93 %add = fadd <2 x float> %mul, %ad94 store <2 x float> %add, ptr %ret, align 1695 br label %for.cond96 }97 98 define void @extracopy(<2 x float> %shuf, <2 x float> %mu, <2 x float> %ad, ptr %ret) #0 {99 unreachable100 }101 102 attributes #0 = { "target-cpu"="cortex-a57" }103 104...105---106name: indexed_2s107alignment: 16108tracksRegLiveness: true109registers:110 - { id: 0, class: fpr64 }111 - { id: 1, class: fpr64 }112 - { id: 2, class: fpr64 }113 - { id: 3, class: fpr64 }114 - { id: 4, class: gpr64common }115 - { id: 5, class: fpr64 }116 - { id: 6, class: fpr64 }117 - { id: 7, class: fpr128 }118 - { id: 8, class: fpr128 }119 - { id: 9, class: fpr64 }120 - { id: 10, class: fpr64 }121liveins:122 - { reg: '$d0', virtual-reg: '%1' }123 - { reg: '$d1', virtual-reg: '%2' }124 - { reg: '$d2', virtual-reg: '%3' }125 - { reg: '$x0', virtual-reg: '%4' }126frameInfo:127 maxAlignment: 1128 maxCallFrameSize: 0129machineFunctionInfo: {}130body: |131 ; CHECK-LABEL: name: indexed_2s132 ; CHECK: bb.0.entry:133 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0136 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2137 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1138 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0139 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF140 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub141 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]142 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]143 ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0144 ; CHECK-NEXT: {{ $}}145 ; CHECK-NEXT: bb.1.for.cond:146 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr147 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr148 ; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)149 ; CHECK-NEXT: B %bb.1150 bb.0.entry:151 liveins: $d0, $d1, $d2, $x0152 153 %4:gpr64common = COPY $x0154 %3:fpr64 = COPY $d2155 %2:fpr64 = COPY $d1156 %1:fpr64 = COPY $d0157 %8:fpr128 = IMPLICIT_DEF158 %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub159 %6:fpr64 = COPY %3160 %5:fpr64 = COPY %2161 %0:fpr64 = DUPv2i32lane killed %7, 0162 163 bb.1.for.cond:164 %9:fpr64 = FMULv2f32 %5, %0, implicit $fpcr165 %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr166 STRDui killed %10, %4, 0 :: (store 8 into %ir.ret, align 16)167 B %bb.1168 169...170---171name: indexed_2s_rev172alignment: 16173tracksRegLiveness: true174registers:175 - { id: 0, class: fpr64 }176 - { id: 1, class: fpr64 }177 - { id: 2, class: fpr64 }178 - { id: 3, class: fpr64 }179 - { id: 4, class: gpr64common }180 - { id: 5, class: fpr64 }181 - { id: 6, class: fpr64 }182 - { id: 7, class: fpr128 }183 - { id: 8, class: fpr128 }184 - { id: 9, class: fpr64 }185 - { id: 10, class: fpr64 }186liveins:187 - { reg: '$d0', virtual-reg: '%1' }188 - { reg: '$d1', virtual-reg: '%2' }189 - { reg: '$d2', virtual-reg: '%3' }190 - { reg: '$x0', virtual-reg: '%4' }191frameInfo:192 maxAlignment: 1193 maxCallFrameSize: 0194machineFunctionInfo: {}195body: |196 ; CHECK-LABEL: name: indexed_2s_rev197 ; CHECK: bb.0.entry:198 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0201 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2202 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1203 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0204 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF205 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub206 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]207 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]208 ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0209 ; CHECK-NEXT: {{ $}}210 ; CHECK-NEXT: bb.1.for.cond:211 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr212 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr213 ; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)214 ; CHECK-NEXT: B %bb.1215 bb.0.entry:216 liveins: $d0, $d1, $d2, $x0217 218 %4:gpr64common = COPY $x0219 %3:fpr64 = COPY $d2220 %2:fpr64 = COPY $d1221 %1:fpr64 = COPY $d0222 %8:fpr128 = IMPLICIT_DEF223 %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub224 %6:fpr64 = COPY %3225 %5:fpr64 = COPY %2226 %0:fpr64 = DUPv2i32lane killed %7, 0227 228 bb.1.for.cond:229 %9:fpr64 = FMULv2f32 %0, %5, implicit $fpcr230 %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr231 STRDui killed %10, %4, 0 :: (store 8 into %ir.ret, align 16)232 B %bb.1233 234...235---236name: indexed_2d237alignment: 16238tracksRegLiveness: true239registers:240 - { id: 0, class: fpr128 }241 - { id: 1, class: fpr128 }242 - { id: 2, class: fpr128 }243 - { id: 3, class: fpr128 }244 - { id: 4, class: gpr64common }245 - { id: 5, class: fpr128 }246 - { id: 6, class: fpr128 }247 - { id: 7, class: fpr128 }248 - { id: 8, class: fpr128 }249liveins:250 - { reg: '$q0', virtual-reg: '%1' }251 - { reg: '$q1', virtual-reg: '%2' }252 - { reg: '$q2', virtual-reg: '%3' }253 - { reg: '$x0', virtual-reg: '%4' }254frameInfo:255 maxAlignment: 1256 maxCallFrameSize: 0257machineFunctionInfo: {}258body: |259 ; CHECK-LABEL: name: indexed_2d260 ; CHECK: bb.0.entry:261 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0262 ; CHECK-NEXT: {{ $}}263 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0264 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2265 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1266 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128 = COPY $q0267 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr128 = COPY [[COPY1]]268 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr128 = COPY [[COPY2]]269 ; CHECK-NEXT: [[DUPv2i64lane:%[0-9]+]]:fpr128 = DUPv2i64lane [[COPY3]], 0270 ; CHECK-NEXT: {{ $}}271 ; CHECK-NEXT: bb.1.for.cond:272 ; CHECK-NEXT: [[FMULv2i64_indexed:%[0-9]+]]:fpr128 = FMULv2i64_indexed [[COPY5]], [[COPY3]], 0, implicit $fpcr273 ; CHECK-NEXT: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 killed [[FMULv2i64_indexed]], [[COPY4]], implicit $fpcr274 ; CHECK-NEXT: STRQui killed [[FADDv2f64_]], [[COPY]], 0 :: (store (s128) into %ir.ret)275 ; CHECK-NEXT: B %bb.1276 bb.0.entry:277 liveins: $q0, $q1, $q2, $x0278 279 %4:gpr64common = COPY $x0280 %3:fpr128 = COPY $q2281 %2:fpr128 = COPY $q1282 %1:fpr128 = COPY $q0283 %6:fpr128 = COPY %3284 %5:fpr128 = COPY %2285 %0:fpr128 = DUPv2i64lane %1, 0286 287 bb.1.for.cond:288 %7:fpr128 = FMULv2f64 %5, %0, implicit $fpcr289 %8:fpr128 = FADDv2f64 killed %7, %6, implicit $fpcr290 STRQui killed %8, %4, 0 :: (store 16 into %ir.ret)291 B %bb.1292 293...294---295name: indexed_4s296alignment: 16297tracksRegLiveness: true298registers:299 - { id: 0, class: fpr128 }300 - { id: 1, class: fpr128 }301 - { id: 2, class: fpr128 }302 - { id: 3, class: fpr128 }303 - { id: 4, class: gpr64common }304 - { id: 5, class: fpr128 }305 - { id: 6, class: fpr128 }306 - { id: 7, class: fpr128 }307 - { id: 8, class: fpr128 }308liveins:309 - { reg: '$q0', virtual-reg: '%1' }310 - { reg: '$q1', virtual-reg: '%2' }311 - { reg: '$q2', virtual-reg: '%3' }312 - { reg: '$x0', virtual-reg: '%4' }313frameInfo:314 maxAlignment: 1315 maxCallFrameSize: 0316machineFunctionInfo: {}317body: |318 ; CHECK-LABEL: name: indexed_4s319 ; CHECK: bb.0.entry:320 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0321 ; CHECK-NEXT: {{ $}}322 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0323 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2324 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1325 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128 = COPY $q0326 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr128 = COPY [[COPY1]]327 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr128 = COPY [[COPY2]]328 ; CHECK-NEXT: [[DUPv4i32lane:%[0-9]+]]:fpr128 = DUPv4i32lane [[COPY3]], 0329 ; CHECK-NEXT: {{ $}}330 ; CHECK-NEXT: bb.1.for.cond:331 ; CHECK-NEXT: [[FMULv4i32_indexed:%[0-9]+]]:fpr128 = FMULv4i32_indexed [[COPY5]], [[COPY3]], 0, implicit $fpcr332 ; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 killed [[FMULv4i32_indexed]], [[COPY4]], implicit $fpcr333 ; CHECK-NEXT: STRQui killed [[FADDv4f32_]], [[COPY]], 0 :: (store (s128) into %ir.ret)334 ; CHECK-NEXT: B %bb.1335 bb.0.entry:336 liveins: $q0, $q1, $q2, $x0337 338 %4:gpr64common = COPY $x0339 %3:fpr128 = COPY $q2340 %2:fpr128 = COPY $q1341 %1:fpr128 = COPY $q0342 %6:fpr128 = COPY %3343 %5:fpr128 = COPY %2344 %0:fpr128 = DUPv4i32lane %1, 0345 346 bb.1.for.cond:347 %7:fpr128 = FMULv4f32 %5, %0, implicit $fpcr348 %8:fpr128 = FADDv4f32 killed %7, %6, implicit $fpcr349 STRQui killed %8, %4, 0 :: (store 16 into %ir.ret)350 B %bb.1351 352...353---354name: indexed_4h355alignment: 16356tracksRegLiveness: true357registers:358 - { id: 0, class: fpr64 }359 - { id: 1, class: fpr64 }360 - { id: 2, class: fpr64 }361 - { id: 3, class: fpr64 }362 - { id: 4, class: gpr64common }363 - { id: 5, class: fpr128 }364 - { id: 6, class: fpr128 }365 - { id: 7, class: fpr64 }366 - { id: 8, class: fpr64 }367liveins:368 - { reg: '$d0', virtual-reg: '%1' }369 - { reg: '$d1', virtual-reg: '%2' }370 - { reg: '$d2', virtual-reg: '%3' }371 - { reg: '$x0', virtual-reg: '%4' }372frameInfo:373 maxAlignment: 1374 maxCallFrameSize: 0375machineFunctionInfo: {}376body: |377 ; CHECK-LABEL: name: indexed_4h378 ; CHECK: bb.0.entry:379 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0380 ; CHECK-NEXT: {{ $}}381 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0382 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2383 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1384 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0385 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF386 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128_lo = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub387 ; CHECK-NEXT: [[DUPv4i16lane:%[0-9]+]]:fpr64 = DUPv4i16lane [[INSERT_SUBREG]], 0388 ; CHECK-NEXT: {{ $}}389 ; CHECK-NEXT: bb.1.for.cond:390 ; CHECK-NEXT: [[FMULv4i16_indexed:%[0-9]+]]:fpr64 = FMULv4i16_indexed [[COPY2]], [[INSERT_SUBREG]], 0, implicit $fpcr391 ; CHECK-NEXT: [[FADDv4f16_:%[0-9]+]]:fpr64 = FADDv4f16 killed [[FMULv4i16_indexed]], [[COPY1]], implicit $fpcr392 ; CHECK-NEXT: STRDui killed [[FADDv4f16_]], [[COPY]], 0 :: (store (s64) into %ir.ret, align 16)393 ; CHECK-NEXT: B %bb.1394 bb.0.entry:395 liveins: $d0, $d1, $d2, $x0396 397 %4:gpr64common = COPY $x0398 %3:fpr64 = COPY $d2399 %2:fpr64 = COPY $d1400 %1:fpr64 = COPY $d0401 %6:fpr128 = IMPLICIT_DEF402 %5:fpr128 = INSERT_SUBREG %6, %1, %subreg.dsub403 %0:fpr64 = DUPv4i16lane killed %5, 0404 405 bb.1.for.cond:406 %7:fpr64 = FMULv4f16 %2, %0, implicit $fpcr407 %8:fpr64 = FADDv4f16 killed %7, %3, implicit $fpcr408 STRDui killed %8, %4, 0 :: (store 8 into %ir.ret, align 16)409 B %bb.1410 411...412---413name: indexed_8h414alignment: 16415tracksRegLiveness: true416registers:417 - { id: 0, class: fpr128 }418 - { id: 1, class: fpr128 }419 - { id: 2, class: fpr128 }420 - { id: 3, class: fpr128 }421 - { id: 4, class: gpr64common }422 - { id: 5, class: fpr128 }423 - { id: 6, class: fpr128 }424liveins:425 - { reg: '$q0', virtual-reg: '%1' }426 - { reg: '$q1', virtual-reg: '%2' }427 - { reg: '$q2', virtual-reg: '%3' }428 - { reg: '$x0', virtual-reg: '%4' }429frameInfo:430 maxAlignment: 1431 maxCallFrameSize: 0432machineFunctionInfo: {}433body: |434 ; CHECK-LABEL: name: indexed_8h435 ; CHECK: bb.0.entry:436 ; CHECK-NEXT: liveins: $q0, $q1, $q2, $x0437 ; CHECK-NEXT: {{ $}}438 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0439 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q2440 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr128 = COPY $q1441 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr128_lo = COPY $q0442 ; CHECK-NEXT: [[DUPv8i16lane:%[0-9]+]]:fpr128 = DUPv8i16lane [[COPY3]], 0443 ; CHECK-NEXT: {{ $}}444 ; CHECK-NEXT: bb.1.for.cond:445 ; CHECK-NEXT: [[FMULv8i16_indexed:%[0-9]+]]:fpr128 = FMULv8i16_indexed [[COPY2]], [[COPY3]], 0, implicit $fpcr446 ; CHECK-NEXT: [[FADDv8f16_:%[0-9]+]]:fpr128 = FADDv8f16 killed [[FMULv8i16_indexed]], [[COPY1]], implicit $fpcr447 ; CHECK-NEXT: STRQui killed [[FADDv8f16_]], [[COPY]], 0 :: (store (s128) into %ir.ret)448 ; CHECK-NEXT: B %bb.1449 bb.0.entry:450 liveins: $q0, $q1, $q2, $x0451 452 %4:gpr64common = COPY $x0453 %3:fpr128 = COPY $q2454 %2:fpr128 = COPY $q1455 %1:fpr128 = COPY $q0456 %0:fpr128 = DUPv8i16lane %1, 0457 458 bb.1.for.cond:459 %5:fpr128 = FMULv8f16 %2, %0, implicit $fpcr460 %6:fpr128 = FADDv8f16 killed %5, %3, implicit $fpcr461 STRQui killed %6, %4, 0 :: (store 16 into %ir.ret)462 B %bb.1463 464...465---466name: kill_state467alignment: 16468tracksRegLiveness: true469registers:470 - { id: 0, class: fpr64 }471 - { id: 1, class: fpr64 }472 - { id: 2, class: fpr64 }473 - { id: 3, class: fpr64 }474 - { id: 4, class: gpr64common }475 - { id: 5, class: gpr64common }476 - { id: 6, class: fpr32 }477 - { id: 7, class: fpr64 }478 - { id: 8, class: fpr64 }479 - { id: 9, class: fpr128 }480 - { id: 10, class: fpr128 }481 - { id: 11, class: fpr128 }482 - { id: 12, class: fpr128 }483 - { id: 13, class: fpr128 }484 - { id: 14, class: fpr64 }485 - { id: 15, class: fpr64 }486 - { id: 16, class: fpr64 }487liveins:488 - { reg: '$d0', virtual-reg: '%1' }489 - { reg: '$d1', virtual-reg: '%2' }490 - { reg: '$d2', virtual-reg: '%3' }491 - { reg: '$x0', virtual-reg: '%4' }492 - { reg: '$x1', virtual-reg: '%5' }493 - { reg: '$s3', virtual-reg: '%6' }494frameInfo:495 maxAlignment: 1496 maxCallFrameSize: 0497machineFunctionInfo: {}498body: |499 ; CHECK-LABEL: name: kill_state500 ; CHECK: bb.0.entry:501 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0, $x1, $s3502 ; CHECK-NEXT: {{ $}}503 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s3504 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1505 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0506 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d2507 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY $d1508 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY $d0509 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF510 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.dsub511 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY [[COPY3]]512 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:fpr64 = COPY [[COPY4]]513 ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0514 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF515 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub516 ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, killed [[INSERT_SUBREG1]], 0517 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub518 ; CHECK-NEXT: STRDui killed [[COPY8]], [[COPY1]], 0 :: (store (s64) into %ir.ret2)519 ; CHECK-NEXT: {{ $}}520 ; CHECK-NEXT: bb.1.for.cond:521 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY7]], [[INSERT_SUBREG]], 0, implicit $fpcr522 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY6]], implicit $fpcr523 ; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY2]], 0 :: (store (s64) into %ir.ret, align 16)524 ; CHECK-NEXT: B %bb.1525 bb.0.entry:526 liveins: $d0, $d1, $d2, $x0, $x1, $s3527 528 %6:fpr32 = COPY $s3529 %5:gpr64common = COPY $x1530 %4:gpr64common = COPY $x0531 %3:fpr64 = COPY $d2532 %2:fpr64 = COPY $d1533 %1:fpr64 = COPY $d0534 %10:fpr128 = IMPLICIT_DEF535 %9:fpr128 = INSERT_SUBREG %10, %1, %subreg.dsub536 %8:fpr64 = COPY %3537 %7:fpr64 = COPY %2538 %0:fpr64 = DUPv2i32lane %9, 0539 %12:fpr128 = IMPLICIT_DEF540 %11:fpr128 = INSERT_SUBREG %12, %6, %subreg.ssub541 %13:fpr128 = INSvi32lane killed %9, 1, killed %11, 0542 %14:fpr64 = COPY %13.dsub543 STRDui killed %14, %5, 0 :: (store (s64) into %ir.ret2)544 545 bb.1.for.cond:546 %15:fpr64 = FMULv2f32 %7, %0, implicit $fpcr547 %16:fpr64 = FADDv2f32 killed %15, %8, implicit $fpcr548 STRDui killed %16, %4, 0 :: (store (s64) into %ir.ret, align 16)549 B %bb.1550 551...552---553name: extracopy554alignment: 16555tracksRegLiveness: true556registers:557 - { id: 0, class: fpr64 }558 - { id: 1, class: fpr64 }559 - { id: 2, class: fpr64 }560 - { id: 3, class: fpr64 }561 - { id: 4, class: gpr64common }562 - { id: 5, class: fpr64 }563 - { id: 6, class: fpr64 }564 - { id: 7, class: fpr128 }565 - { id: 8, class: fpr128 }566 - { id: 9, class: fpr64 }567 - { id: 10, class: fpr64 }568 - { id: 11, class: fpr64 }569liveins:570 - { reg: '$d0', virtual-reg: '%1' }571 - { reg: '$d1', virtual-reg: '%2' }572 - { reg: '$d2', virtual-reg: '%3' }573 - { reg: '$x0', virtual-reg: '%4' }574frameInfo:575 maxAlignment: 1576 maxCallFrameSize: 0577machineFunctionInfo: {}578body: |579 ; CHECK-LABEL: name: extracopy580 ; CHECK: bb.0:581 ; CHECK-NEXT: liveins: $d0, $d1, $d2, $x0582 ; CHECK-NEXT: {{ $}}583 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0584 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d2585 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1586 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d0587 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF588 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY3]], %subreg.dsub589 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr64 = COPY [[COPY1]]590 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:fpr64 = COPY [[COPY2]]591 ; CHECK-NEXT: [[DUPv2i32lane:%[0-9]+]]:fpr64 = DUPv2i32lane [[INSERT_SUBREG]], 0592 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:fpr64 = COPY [[DUPv2i32lane]]593 ; CHECK-NEXT: {{ $}}594 ; CHECK-NEXT: bb.1:595 ; CHECK-NEXT: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY5]], [[INSERT_SUBREG]], 0, implicit $fpcr596 ; CHECK-NEXT: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 killed [[FMULv2i32_indexed]], [[COPY4]], implicit $fpcr597 ; CHECK-NEXT: STRDui killed [[FADDv2f32_]], [[COPY]], 0 :: (store (s64), align 16)598 ; CHECK-NEXT: B %bb.1599 bb.0:600 liveins: $d0, $d1, $d2, $x0601 602 %4:gpr64common = COPY $x0603 %3:fpr64 = COPY $d2604 %2:fpr64 = COPY $d1605 %1:fpr64 = COPY $d0606 %8:fpr128 = IMPLICIT_DEF607 %7:fpr128 = INSERT_SUBREG %8, %1, %subreg.dsub608 %6:fpr64 = COPY %3609 %5:fpr64 = COPY %2610 %11:fpr64 = DUPv2i32lane killed %7, 0611 %0:fpr64 = COPY %11612 613 bb.1:614 %9:fpr64 = FMULv2f32 %5, %0, implicit $fpcr615 %10:fpr64 = FADDv2f32 killed %9, %6, implicit $fpcr616 STRDui killed %10, %4, 0 :: (store 8, align 16)617 B %bb.1618 619...620