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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=arm64-appe-ios -o - -run-pass=machine-combiner %s | FileCheck %s3 4--- |5 define float @reassoicate_some_inputs_in_different_block(ptr %a, i1 %c) {6 ret float undef7 }8 9 define float @reassoicate_candidates_in_different_blocks(ptr %a, i1 %c) {10 ret float undef11 }12 13 define float @reassoicate_candidates_in_different_blocks_no_sink(ptr %a, i1 %c) {14 ret float undef15 }16 17 define float @no_reassociate_different_block(ptr %a, i1 %c) {18 ret float undef19 }20 21 declare void @use()22 23 24...25# FIXME: Should reassociate the serialized reduction in bb.1 to improve parallelism.26---27name: reassoicate_some_inputs_in_different_block28alignment: 429tracksRegLiveness: true30body: |31 ; CHECK-LABEL: name: reassoicate_some_inputs_in_different_block32 ; CHECK: bb.0:33 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)34 ; CHECK-NEXT: liveins: $x0, $w135 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w137 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x038 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128), align 4)39 ; CHECK-NEXT: [[LDRQui1:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 1 :: (load (s128), align 4)40 ; CHECK-NEXT: [[LDRQui2:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 2 :: (load (s128), align 4)41 ; CHECK-NEXT: [[LDRQui3:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 4 :: (load (s128), align 4)42 ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.243 ; CHECK-NEXT: B %bb.144 ; CHECK-NEXT: {{ $}}45 ; CHECK-NEXT: bb.1:46 ; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui]], [[LDRQui2]], implicit $fpcr47 ; CHECK-NEXT: [[FADDv4f32_1:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui3]], [[LDRQui1]], implicit $fpcr48 ; CHECK-NEXT: [[FADDv4f32_2:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 killed [[FADDv4f32_1]], killed [[FADDv4f32_]], implicit $fpcr49 ; CHECK-NEXT: [[FADDPv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDPv4f32 [[FADDv4f32_2]], [[FADDv4f32_2]], implicit $fpcr50 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[FADDPv4f32_]].dsub51 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY2]]52 ; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed [[COPY3]], implicit $fpcr53 ; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]54 ; CHECK-NEXT: RET_ReallyLR implicit $s055 ; CHECK-NEXT: {{ $}}56 ; CHECK-NEXT: bb.2:57 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]58 ; CHECK-NEXT: $q1 = COPY [[LDRQui2]]59 ; CHECK-NEXT: $q2 = COPY [[LDRQui1]]60 ; CHECK-NEXT: $q3 = COPY [[LDRQui3]]61 ; CHECK-NEXT: TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q362 bb.0:63 successors: %bb.1, %bb.264 liveins: $x0, $w165 66 %5:gpr32 = COPY $w167 %4:gpr64common = COPY $x068 %0:fpr128 = LDRQui %4, 0 :: (load (s128), align 4)69 %1:fpr128 = LDRQui %4, 1 :: (load (s128), align 4)70 %2:fpr128 = LDRQui %4, 2 :: (load (s128), align 4)71 %3:fpr128 = LDRQui %4, 4 :: (load (s128), align 4)72 TBZW %5, 0, %bb.273 B %bb.174 75 bb.1:76 %6:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %0, %2, implicit $fpcr77 %7:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %1, killed %6, implicit $fpcr78 %8:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %3, killed %7, implicit $fpcr79 %9:fpr128 = nofpexcept FADDPv4f32 %8, %8, implicit $fpcr80 %10:gpr64all = COPY %9.dsub81 %12:fpr64 = COPY %1082 %11:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed %12, implicit $fpcr83 $s0 = COPY %1184 RET_ReallyLR implicit $s085 86 bb.2:87 $q0 = COPY %088 $q1 = COPY %289 $q2 = COPY %190 $q3 = COPY %391 TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q392 93...94# Variation of reassoicate_some_inputs_in_different_block where the candidate95# instructions are split across 2 blocks.96---97name: reassoicate_candidates_in_different_blocks98alignment: 499tracksRegLiveness: true100body: |101 ; CHECK-LABEL: name: reassoicate_candidates_in_different_blocks102 ; CHECK: bb.0:103 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)104 ; CHECK-NEXT: liveins: $x0, $w1105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1107 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0108 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128), align 4)109 ; CHECK-NEXT: [[LDRQui1:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 1 :: (load (s128), align 4)110 ; CHECK-NEXT: [[LDRQui2:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 2 :: (load (s128), align 4)111 ; CHECK-NEXT: [[LDRQui3:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 4 :: (load (s128), align 4)112 ; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui]], [[LDRQui2]], implicit $fpcr113 ; CHECK-NEXT: [[FADDv4f32_1:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui1]], killed [[FADDv4f32_]], implicit $fpcr114 ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.2115 ; CHECK-NEXT: B %bb.1116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: bb.1:118 ; CHECK-NEXT: [[FADDv4f32_2:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui3]], killed [[FADDv4f32_1]], implicit $fpcr119 ; CHECK-NEXT: [[FADDPv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDPv4f32 [[FADDv4f32_2]], [[FADDv4f32_2]], implicit $fpcr120 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[FADDPv4f32_]].dsub121 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY2]]122 ; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed [[COPY3]], implicit $fpcr123 ; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]124 ; CHECK-NEXT: RET_ReallyLR implicit $s0125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: bb.2:127 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]128 ; CHECK-NEXT: $q1 = COPY [[LDRQui2]]129 ; CHECK-NEXT: $q2 = COPY [[LDRQui1]]130 ; CHECK-NEXT: $q3 = COPY [[LDRQui3]]131 ; CHECK-NEXT: TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3132 bb.0:133 successors: %bb.1, %bb.2134 liveins: $x0, $w1135 136 %5:gpr32 = COPY $w1137 %4:gpr64common = COPY $x0138 %0:fpr128 = LDRQui %4, 0 :: (load (s128), align 4)139 %1:fpr128 = LDRQui %4, 1 :: (load (s128), align 4)140 %2:fpr128 = LDRQui %4, 2 :: (load (s128), align 4)141 %3:fpr128 = LDRQui %4, 4 :: (load (s128), align 4)142 %6:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %0, %2, implicit $fpcr143 %7:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %1, killed %6, implicit $fpcr144 TBZW %5, 0, %bb.2145 B %bb.1146 147 bb.1:148 %8:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %3, killed %7, implicit $fpcr149 %9:fpr128 = nofpexcept FADDPv4f32 %8, %8, implicit $fpcr150 %10:gpr64all = COPY %9.dsub151 %12:fpr64 = COPY %10152 %11:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed %12, implicit $fpcr153 $s0 = COPY %11154 RET_ReallyLR implicit $s0155 156 bb.2:157 $q0 = COPY %0158 $q1 = COPY %2159 $q2 = COPY %1160 $q3 = COPY %3161 TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3162 163...164 165---166name: reassoicate_candidates_in_different_blocks_no_sink167alignment: 4168tracksRegLiveness: true169body: |170 ; CHECK-LABEL: name: reassoicate_candidates_in_different_blocks_no_sink171 ; CHECK: bb.0:172 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)173 ; CHECK-NEXT: liveins: $x0, $w1174 ; CHECK-NEXT: {{ $}}175 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1176 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0177 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128), align 4)178 ; CHECK-NEXT: [[LDRQui1:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 1 :: (load (s128), align 4)179 ; CHECK-NEXT: [[LDRQui2:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 2 :: (load (s128), align 4)180 ; CHECK-NEXT: [[LDRQui3:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 4 :: (load (s128), align 4)181 ; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui]], [[LDRQui2]], implicit $fpcr182 ; CHECK-NEXT: [[FADDv4f32_1:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui1]], killed [[FADDv4f32_]], implicit $fpcr183 ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.2184 ; CHECK-NEXT: B %bb.1185 ; CHECK-NEXT: {{ $}}186 ; CHECK-NEXT: bb.1:187 ; CHECK-NEXT: [[FADDv4f32_2:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui3]], killed [[FADDv4f32_1]], implicit $fpcr188 ; CHECK-NEXT: [[FADDPv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDPv4f32 [[FADDv4f32_2]], [[FADDv4f32_2]], implicit $fpcr189 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[FADDPv4f32_]].dsub190 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY2]]191 ; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed [[COPY3]], implicit $fpcr192 ; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]193 ; CHECK-NEXT: RET_ReallyLR implicit $s0194 ; CHECK-NEXT: {{ $}}195 ; CHECK-NEXT: bb.2:196 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]197 ; CHECK-NEXT: $q1 = COPY [[LDRQui2]]198 ; CHECK-NEXT: $q2 = COPY [[LDRQui1]]199 ; CHECK-NEXT: $q3 = COPY [[FADDv4f32_1]]200 ; CHECK-NEXT: TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3201 bb.0:202 successors: %bb.1, %bb.2203 liveins: $x0, $w1204 205 %5:gpr32 = COPY $w1206 %4:gpr64common = COPY $x0207 %0:fpr128 = LDRQui %4, 0 :: (load (s128), align 4)208 %1:fpr128 = LDRQui %4, 1 :: (load (s128), align 4)209 %2:fpr128 = LDRQui %4, 2 :: (load (s128), align 4)210 %3:fpr128 = LDRQui %4, 4 :: (load (s128), align 4)211 %6:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %0, %2, implicit $fpcr212 %7:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %1, killed %6, implicit $fpcr213 TBZW %5, 0, %bb.2214 B %bb.1215 216 bb.1:217 %8:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %3, killed %7, implicit $fpcr218 %9:fpr128 = nofpexcept FADDPv4f32 %8, %8, implicit $fpcr219 %10:gpr64all = COPY %9.dsub220 %12:fpr64 = COPY %10221 %11:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed %12, implicit $fpcr222 $s0 = COPY %11223 RET_ReallyLR implicit $s0224 225 bb.2:226 $q0 = COPY %0227 $q1 = COPY %2228 $q2 = COPY %1229 $q3 = COPY %7230 TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3231 232...233 234# Reassociation of the reduction in bb.1 is not profitable, because LDRQui3 has a235# much larger latency than the other loads.236---237name: no_reassociate_different_block238alignment: 4239tracksRegLiveness: true240body: |241 ; CHECK-LABEL: name: no_reassociate_different_block242 ; CHECK: bb.0:243 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)244 ; CHECK-NEXT: liveins: $x0, $w1245 ; CHECK-NEXT: {{ $}}246 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1247 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0248 ; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128), align 4)249 ; CHECK-NEXT: [[LDRQui1:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 1 :: (load (s128), align 4)250 ; CHECK-NEXT: [[LDRQui2:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 2 :: (load (s128), align 4)251 ; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY1]], 8 :: (load (s64))252 ; CHECK-NEXT: [[LDRXui1:%[0-9]+]]:gpr64common = LDRXui killed [[LDRXui]], 0 :: (load (s64))253 ; CHECK-NEXT: [[LDRQui3:%[0-9]+]]:fpr128 = LDRQui killed [[LDRXui1]], 0 :: (load (s128), align 4)254 ; CHECK-NEXT: TBZW [[COPY]], 0, %bb.2255 ; CHECK-NEXT: B %bb.1256 ; CHECK-NEXT: {{ $}}257 ; CHECK-NEXT: bb.1:258 ; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui]], [[LDRQui2]], implicit $fpcr259 ; CHECK-NEXT: [[FADDv4f32_1:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui1]], killed [[FADDv4f32_]], implicit $fpcr260 ; CHECK-NEXT: [[FADDv4f32_2:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui3]], killed [[FADDv4f32_1]], implicit $fpcr261 ; CHECK-NEXT: [[FADDPv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDPv4f32 [[FADDv4f32_2]], [[FADDv4f32_2]], implicit $fpcr262 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[FADDPv4f32_]].dsub263 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY2]]264 ; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed [[COPY3]], implicit $fpcr265 ; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]266 ; CHECK-NEXT: RET_ReallyLR implicit $s0267 ; CHECK-NEXT: {{ $}}268 ; CHECK-NEXT: bb.2:269 ; CHECK-NEXT: $q0 = COPY [[LDRQui]]270 ; CHECK-NEXT: $q1 = COPY [[LDRQui2]]271 ; CHECK-NEXT: $q2 = COPY [[LDRQui1]]272 ; CHECK-NEXT: $q3 = COPY [[LDRQui3]]273 ; CHECK-NEXT: TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3274 bb.0:275 successors: %bb.1, %bb.2276 liveins: $x0, $w1277 278 %5:gpr32 = COPY $w1279 %4:gpr64common = COPY $x0280 %0:fpr128 = LDRQui %4, 0 :: (load (s128), align 4)281 %1:fpr128 = LDRQui %4, 1 :: (load (s128), align 4)282 %2:fpr128 = LDRQui %4, 2 :: (load (s128), align 4)283 %6:gpr64common = LDRXui %4, 8 :: (load (s64))284 %7:gpr64common = LDRXui killed %6, 0 :: (load (s64))285 %3:fpr128 = LDRQui killed %7, 0 :: (load (s128), align 4)286 TBZW %5, 0, %bb.2287 B %bb.1288 289 bb.1:290 %8:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %0, %2, implicit $fpcr291 %9:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %1, killed %8, implicit $fpcr292 %10:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %3, killed %9, implicit $fpcr293 %11:fpr128 = nofpexcept FADDPv4f32 %10, %10, implicit $fpcr294 %12:gpr64all = COPY %11.dsub295 %14:fpr64 = COPY %12296 %13:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed %14, implicit $fpcr297 $s0 = COPY %13298 RET_ReallyLR implicit $s0299 300 bb.2:301 $q0 = COPY %0302 $q1 = COPY %2303 $q2 = COPY %1304 $q3 = COPY %3305 TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3306 307...308