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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s3 4; The test cases in this file check following transformation if the right form5; can reduce latency.6;     A - (B + C)  ==>   (A - B) - C7 8; 32 bit version.9define i32 @test1(i32 %a, i32 %b, i32 %c) {10; CHECK-LABEL: test1:11; CHECK:       // %bb.0: // %entry12; CHECK-NEXT:    add w8, w0, #10013; CHECK-NEXT:    orr w9, w2, #0x8014; CHECK-NEXT:    eor w10, w1, w8, lsl #815; CHECK-NEXT:    sub w8, w9, w816; CHECK-NEXT:    sub w8, w8, w1017; CHECK-NEXT:    eor w0, w8, w10, asr #1318; CHECK-NEXT:    ret19entry:20  %c1  = or  i32 %c, 12821  %a1  = add i32 %a, 10022  %shl = shl i32 %a1, 823  %xor = xor i32 %shl, %b24  %add = add i32 %xor, %a125  %sub = sub i32 %c1, %add26  %shr = ashr i32 %xor, 1327  %xor2 = xor i32 %sub, %shr28  ret i32 %xor229}30 31; 64 bit version.32define i64 @test2(i64 %a, i64 %b, i64 %c) {33; CHECK-LABEL: test2:34; CHECK:       // %bb.0: // %entry35; CHECK-NEXT:    add x8, x0, #10036; CHECK-NEXT:    orr x9, x2, #0x8037; CHECK-NEXT:    eor x10, x1, x8, lsl #838; CHECK-NEXT:    sub x8, x9, x839; CHECK-NEXT:    sub x8, x8, x1040; CHECK-NEXT:    eor x0, x8, x10, asr #1341; CHECK-NEXT:    ret42entry:43  %c1  = or  i64 %c, 12844  %a1  = add i64 %a, 10045  %shl = shl i64 %a1, 846  %xor = xor i64 %shl, %b47  %add = add i64 %xor, %a148  %sub = sub i64 %c1, %add49  %shr = ashr i64 %xor, 1350  %xor2 = xor i64 %sub, %shr51  ret i64 %xor252}53 54; Negative test. The right form can't reduce latency.55define i32 @test3(i32 %a, i32 %b, i32 %c) {56; CHECK-LABEL: test3:57; CHECK:       // %bb.0: // %entry58; CHECK-NEXT:    add w8, w0, #10059; CHECK-NEXT:    orr w9, w2, #0x8060; CHECK-NEXT:    eor w10, w1, w8, lsl #861; CHECK-NEXT:    add w8, w9, w862; CHECK-NEXT:    sub w8, w10, w863; CHECK-NEXT:    eor w0, w8, w10, asr #1364; CHECK-NEXT:    ret65entry:66  %c1  = or  i32 %c, 12867  %a1  = add i32 %a, 10068  %shl = shl i32 %a1, 869  %xor = xor i32 %shl, %b70  %add = add i32 %c1, %a171  %sub = sub i32 %xor, %add72  %shr = ashr i32 %xor, 1373  %xor2 = xor i32 %sub, %shr74  ret i32 %xor275}76 77