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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s3 4; When lowering the LLVM IR to MIR, transient COPY instructions are generated5; to copy parameters from physical registers to virtual registers. Wrong6; handling of transient instructions in MachineCombiner can fail the forllowing7; transformation.8; A - (B + C) ==> (A - B) - C9 10; 32 bit version.11define i32 @test1(i32 %a, i32 %b, i32 %c) {12; CHECK-LABEL: test1:13; CHECK: // %bb.0: // %entry14; CHECK-NEXT: eor w8, w1, w0, lsl #815; CHECK-NEXT: sub w9, w2, w016; CHECK-NEXT: sub w9, w9, w817; CHECK-NEXT: eor w0, w9, w8, asr #1318; CHECK-NEXT: ret19entry:20 %shl = shl i32 %a, 821 %xor = xor i32 %shl, %b22 %add = add i32 %xor, %a23 %sub = sub i32 %c, %add24 %shr = ashr i32 %xor, 1325 %xor2 = xor i32 %sub, %shr26 ret i32 %xor227}28 29; 64 bit version.30define i64 @test2(i64 %a, i64 %b, i64 %c) {31; CHECK-LABEL: test2:32; CHECK: // %bb.0: // %entry33; CHECK-NEXT: eor x8, x1, x0, lsl #834; CHECK-NEXT: sub x9, x2, x035; CHECK-NEXT: sub x9, x9, x836; CHECK-NEXT: eor x0, x9, x8, asr #1337; CHECK-NEXT: ret38entry:39 %shl = shl i64 %a, 840 %xor = xor i64 %shl, %b41 %add = add i64 %xor, %a42 %sub = sub i64 %c, %add43 %shr = ashr i64 %xor, 1344 %xor2 = xor i64 %sub, %shr45 ret i64 %xor246}47