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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ISEL3; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-FAST4 5; Test that we use the correct register class.6define i32 @mul_add_imm(i32 %a, i32 %b) {7; CHECK-LABEL: mul_add_imm:8; CHECK: ; %bb.0:9; CHECK-NEXT: mov w8, #4 ; =0x410; CHECK-NEXT: madd w0, w0, w1, w811; CHECK-NEXT: ret12 %1 = mul i32 %a, %b13 %2 = add i32 %1, 414 ret i32 %215}16 17define i32 @mul_sub_imm1(i32 %a, i32 %b) {18; CHECK-LABEL: mul_sub_imm1:19; CHECK: ; %bb.0:20; CHECK-NEXT: mov w8, #4 ; =0x421; CHECK-NEXT: msub w0, w0, w1, w822; CHECK-NEXT: ret23 %1 = mul i32 %a, %b24 %2 = sub i32 4, %125 ret i32 %226}27 28; bugpoint reduced test case. This only tests that we pass the MI verifier.29define void @mul_add_imm2() {30; CHECK-ISEL-LABEL: mul_add_imm2:31; CHECK-ISEL: ; %bb.0: ; %entry32; CHECK-ISEL-NEXT: mov w8, #1 ; =0x133; CHECK-ISEL-NEXT: LBB2_1: ; %for.body834; CHECK-ISEL-NEXT: ; =>This Inner Loop Header: Depth=135; CHECK-ISEL-NEXT: cbnz w8, LBB2_136; CHECK-ISEL-NEXT: ; %bb.2: ; %for.end2037; CHECK-ISEL-NEXT: ret38;39; CHECK-FAST-LABEL: mul_add_imm2:40; CHECK-FAST: ; %bb.0: ; %entry41; CHECK-FAST-NEXT: mov x8, #-3 ; =0xfffffffffffffffd42; CHECK-FAST-NEXT: mov x9, #45968 ; =0xb39043; CHECK-FAST-NEXT: madd x8, x8, x8, x844; CHECK-FAST-NEXT: movk x9, #48484, lsl #1645; CHECK-FAST-NEXT: movk x9, #323, lsl #3246; CHECK-FAST-NEXT: LBB2_1: ; %for.body847; CHECK-FAST-NEXT: ; =>This Inner Loop Header: Depth=148; CHECK-FAST-NEXT: cmp x8, x949; CHECK-FAST-NEXT: b.lt LBB2_150; CHECK-FAST-NEXT: ; %bb.2: ; %for.end2051; CHECK-FAST-NEXT: ret52entry:53 br label %for.body54for.body:55 br i1 poison, label %for.body, label %for.body856for.body8:57 %0 = mul i64 undef, -358 %mul1971 = add i64 %0, -359 %cmp7 = icmp slt i64 %mul1971, 139045193000060 br i1 %cmp7, label %for.body8, label %for.end2061for.end20:62 ret void63}64 65define i32 @add1_mul_val1(i32 %a, i32 %b) {66; CHECK-ISEL-LABEL: add1_mul_val1:67; CHECK-ISEL: ; %bb.0:68; CHECK-ISEL-NEXT: madd w0, w1, w0, w169; CHECK-ISEL-NEXT: ret70;71; CHECK-FAST-LABEL: add1_mul_val1:72; CHECK-FAST: ; %bb.0:73; CHECK-FAST-NEXT: add w8, w0, #174; CHECK-FAST-NEXT: mul w0, w8, w175; CHECK-FAST-NEXT: ret76 %1 = add i32 %a, 177 %2 = mul i32 %1, %b78 ret i32 %279}80 81define i32 @add1_mul_val2(i32 %a, i32 %b) {82; CHECK-ISEL-LABEL: add1_mul_val2:83; CHECK-ISEL: ; %bb.0:84; CHECK-ISEL-NEXT: madd w0, w0, w1, w085; CHECK-ISEL-NEXT: ret86;87; CHECK-FAST-LABEL: add1_mul_val2:88; CHECK-FAST: ; %bb.0:89; CHECK-FAST-NEXT: add w8, w1, #190; CHECK-FAST-NEXT: mul w0, w0, w891; CHECK-FAST-NEXT: ret92 %1 = add i32 %b, 193 %2 = mul i32 %a, %194 ret i32 %295}96 97define i64 @add1_mul_val3(i64 %a, i64 %b) {98; CHECK-ISEL-LABEL: add1_mul_val3:99; CHECK-ISEL: ; %bb.0:100; CHECK-ISEL-NEXT: madd x0, x0, x1, x0101; CHECK-ISEL-NEXT: ret102;103; CHECK-FAST-LABEL: add1_mul_val3:104; CHECK-FAST: ; %bb.0:105; CHECK-FAST-NEXT: add x8, x1, #1106; CHECK-FAST-NEXT: mul x0, x0, x8107; CHECK-FAST-NEXT: ret108 %1 = add i64 %b, 1109 %2 = mul i64 %a, %1110 ret i64 %2111}112 113define i64 @add1_mul_val4(i64 %a, i64 %b, i64 %c) {114; CHECK-ISEL-LABEL: add1_mul_val4:115; CHECK-ISEL: ; %bb.0:116; CHECK-ISEL-NEXT: add x8, x0, x2117; CHECK-ISEL-NEXT: madd x0, x8, x1, x8118; CHECK-ISEL-NEXT: ret119;120; CHECK-FAST-LABEL: add1_mul_val4:121; CHECK-FAST: ; %bb.0:122; CHECK-FAST-NEXT: add x8, x0, x2123; CHECK-FAST-NEXT: add x9, x1, #1124; CHECK-FAST-NEXT: mul x0, x8, x9125; CHECK-FAST-NEXT: ret126 %1 = add i64 %a, %c127 %2 = add i64 %b, 1128 %3 = mul i64 %1, %2129 ret i64 %3130}131 132define i32 @sub1_mul_val1(i32 %a, i32 %b) {133; CHECK-ISEL-LABEL: sub1_mul_val1:134; CHECK-ISEL: ; %bb.0:135; CHECK-ISEL-NEXT: msub w0, w1, w0, w1136; CHECK-ISEL-NEXT: ret137;138; CHECK-FAST-LABEL: sub1_mul_val1:139; CHECK-FAST: ; %bb.0:140; CHECK-FAST-NEXT: mov w8, #1 ; =0x1141; CHECK-FAST-NEXT: sub w8, w8, w0142; CHECK-FAST-NEXT: mul w0, w8, w1143; CHECK-FAST-NEXT: ret144 %1 = sub i32 1, %a145 %2 = mul i32 %1, %b146 ret i32 %2147}148 149define i32 @sub1_mul_val2(i32 %a, i32 %b) {150; CHECK-ISEL-LABEL: sub1_mul_val2:151; CHECK-ISEL: ; %bb.0:152; CHECK-ISEL-NEXT: msub w0, w0, w1, w0153; CHECK-ISEL-NEXT: ret154;155; CHECK-FAST-LABEL: sub1_mul_val2:156; CHECK-FAST: ; %bb.0:157; CHECK-FAST-NEXT: mov w8, #1 ; =0x1158; CHECK-FAST-NEXT: sub w8, w8, w1159; CHECK-FAST-NEXT: mul w0, w0, w8160; CHECK-FAST-NEXT: ret161 %1 = sub i32 1, %b162 %2 = mul i32 %a, %1163 ret i32 %2164}165 166define i64 @sub1_mul_val3(i64 %a, i64 %b) {167; CHECK-ISEL-LABEL: sub1_mul_val3:168; CHECK-ISEL: ; %bb.0:169; CHECK-ISEL-NEXT: msub x0, x0, x1, x0170; CHECK-ISEL-NEXT: ret171;172; CHECK-FAST-LABEL: sub1_mul_val3:173; CHECK-FAST: ; %bb.0:174; CHECK-FAST-NEXT: mov x8, #1 ; =0x1175; CHECK-FAST-NEXT: sub x8, x8, x1176; CHECK-FAST-NEXT: mul x0, x0, x8177; CHECK-FAST-NEXT: ret178 %1 = sub i64 1, %b179 %2 = mul i64 %a, %1180 ret i64 %2181}182 183define i64 @sub1_mul_val4(i64 %a, i64 %b) {184; CHECK-ISEL-LABEL: sub1_mul_val4:185; CHECK-ISEL: ; %bb.0:186; CHECK-ISEL-NEXT: sub x8, x0, #1187; CHECK-ISEL-NEXT: msub x0, x8, x1, x8188; CHECK-ISEL-NEXT: ret189;190; CHECK-FAST-LABEL: sub1_mul_val4:191; CHECK-FAST: ; %bb.0:192; CHECK-FAST-NEXT: mov x8, #1 ; =0x1193; CHECK-FAST-NEXT: sub x9, x0, #1194; CHECK-FAST-NEXT: sub x8, x8, x1195; CHECK-FAST-NEXT: mul x0, x9, x8196; CHECK-FAST-NEXT: ret197 %1 = sub i64 %a, 1198 %2 = sub i64 1, %b199 %3 = mul i64 %1, %2200 ret i64 %3201}202 203