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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s3 4; Test code generation support for SUBS (shifted register) from masked integer5; compare sequences. These sequences appear in isinf tests, for example.6 7define i1 @combine_masked_i32(i32 %x) {8; CHECK-LABEL: combine_masked_i32:9; CHECK: // %bb.0:10; CHECK-NEXT: mov w8, #-16777216 // =0xff00000011; CHECK-NEXT: cmp w8, w0, lsl #112; CHECK-NEXT: cset w0, eq13; CHECK-NEXT: ret14 %and = and i32 %x, u0x7fffffff15 %sub = sub i32 %and, u0x7f80000016 %cmp = icmp eq i32 %sub, 017 ret i1 %cmp18}19 20define i1 @combine_masked_i64(i64 %x) {21; CHECK-LABEL: combine_masked_i64:22; CHECK: // %bb.0:23; CHECK-NEXT: mov x8, #-9007199254740992 // =0xffe000000000000024; CHECK-NEXT: cmp x8, x0, lsl #125; CHECK-NEXT: cset w0, eq26; CHECK-NEXT: ret27 %and = and i64 %x, u0x7fffffffffffffff28 %sub = sub i64 %and, u0x7ff000000000000029 %cmp = icmp eq i64 %sub, 030 ret i1 %cmp31}32 33define i1 @combine_masked_ne(i32 %x) {34; CHECK-LABEL: combine_masked_ne:35; CHECK: // %bb.0:36; CHECK-NEXT: mov w8, #-16777216 // =0xff00000037; CHECK-NEXT: cmp w8, w0, lsl #138; CHECK-NEXT: cset w0, ne39; CHECK-NEXT: ret40 %and = and i32 %x, u0x7fffffff41 %cmp = icmp ne i32 %and, u0x7f80000042 ret i1 %cmp43}44 45define i1 @combine_masked_lsl4(i32 %x) {46; CHECK-LABEL: combine_masked_lsl4:47; CHECK: // %bb.0:48; CHECK-NEXT: mov w8, #-134217728 // =0xf800000049; CHECK-NEXT: cmp w8, w0, lsl #450; CHECK-NEXT: cset w0, eq51; CHECK-NEXT: ret52 %and = and i32 %x, u0x0fffffff53 %cmp = icmp eq i32 %and, u0x0f80000054 ret i1 %cmp55}56 57define i1 @dont_combine_not_mask(i32 %x) {58; CHECK-LABEL: dont_combine_not_mask:59; CHECK: // %bb.0:60; CHECK-NEXT: mov w8, #2139095040 // =0x7f80000061; CHECK-NEXT: and w9, w0, #0x7ffffffe62; CHECK-NEXT: cmp w9, w863; CHECK-NEXT: cset w0, eq64; CHECK-NEXT: ret65 %and = and i32 %x, u0x7ffffffe66 %cmp = icmp eq i32 %and, u0x7f80000067 ret i1 %cmp68}69 70define i1 @dont_combine_cmp_not_masked(i32 %x) {71; CHECK-LABEL: dont_combine_cmp_not_masked:72; CHECK: // %bb.0:73; CHECK-NEXT: mov w8, #2139095040 // =0x7f80000074; CHECK-NEXT: and w9, w0, #0x3fffffff75; CHECK-NEXT: cmp w9, w876; CHECK-NEXT: cset w0, eq77; CHECK-NEXT: ret78 %and = and i32 %x, u0x3fffffff79 %cmp = icmp eq i32 %and, u0x7f80000080 ret i1 %cmp81}82 83define i1 @dont_combine_not_constant_mask(i32 %x, i32 %m) {84; CHECK-LABEL: dont_combine_not_constant_mask:85; CHECK: // %bb.0:86; CHECK-NEXT: mov w8, #2139095040 // =0x7f80000087; CHECK-NEXT: and w9, w0, w188; CHECK-NEXT: cmp w9, w889; CHECK-NEXT: cset w0, eq90; CHECK-NEXT: ret91 %and = and i32 %x, %m92 %cmp = icmp eq i32 %and, u0x7f80000093 ret i1 %cmp94}95 96define i1 @dont_combine_not_constant_cmp(i32 %x, i32 %c) {97; CHECK-LABEL: dont_combine_not_constant_cmp:98; CHECK: // %bb.0:99; CHECK-NEXT: and w8, w0, #0xfffffff100; CHECK-NEXT: cmp w8, w1101; CHECK-NEXT: cset w0, eq102; CHECK-NEXT: ret103 %and = and i32 %x, u0x0fffffff104 %cmp = icmp eq i32 %and, %c105 ret i1 %cmp106}107 108define i1 @dont_combine_subs_imm(i32 %x) {109; CHECK-LABEL: dont_combine_subs_imm:110; CHECK: // %bb.0:111; CHECK-NEXT: and w8, w0, #0x7fffffff112; CHECK-NEXT: cmp w8, #291113; CHECK-NEXT: cset w0, eq114; CHECK-NEXT: ret115 %and = and i32 %x, u0x7fffffff116 %cmp = icmp eq i32 %and, u0x123117 ret i1 %cmp118}119 120define i1 @dont_combine_subs_imm_lsl12(i32 %x) {121; CHECK-LABEL: dont_combine_subs_imm_lsl12:122; CHECK: // %bb.0:123; CHECK-NEXT: and w8, w0, #0x7fffffff124; CHECK-NEXT: cmp w8, #291, lsl #12 // =1191936125; CHECK-NEXT: cset w0, eq126; CHECK-NEXT: ret127 %and = and i32 %x, u0x7fffffff128 %cmp = icmp eq i32 %and, u0x123000129 ret i1 %cmp130}131 132define { i1, i1 } @dont_combine_multi_use_cmp(i32 %x) {133; CHECK-LABEL: dont_combine_multi_use_cmp:134; CHECK: // %bb.0:135; CHECK-NEXT: mov w8, #2139095040 // =0x7f800000136; CHECK-NEXT: and w9, w0, #0x7fffffff137; CHECK-NEXT: cmp w9, w8138; CHECK-NEXT: cset w0, eq139; CHECK-NEXT: cset w1, lt140; CHECK-NEXT: ret141 %and = and i32 %x, u0x7fffffff142 %eq = icmp eq i32 %and, u0x7f800000143 %lt = icmp slt i32 %and, u0x7f800000144 %r1 = insertvalue { i1, i1 } poison, i1 %eq, 0145 %r2 = insertvalue { i1, i1 } %r1, i1 %lt, 1146 ret { i1, i1 } %r2147}148 149define { i32, i1 } @dont_combine_multi_use_sub(i32 %x) {150; CHECK-LABEL: dont_combine_multi_use_sub:151; CHECK: // %bb.0:152; CHECK-NEXT: mov w8, #-2139095040 // =0x80800000153; CHECK-NEXT: and w9, w0, #0x7fffffff154; CHECK-NEXT: adds w0, w9, w8155; CHECK-NEXT: cset w1, eq156; CHECK-NEXT: ret157 %and = and i32 %x, u0x7fffffff158 %sub = sub i32 %and, u0x7f800000159 %cmp = icmp eq i32 %sub, 0160 %r1 = insertvalue { i32, i1 } poison, i32 %sub, 0161 %r2 = insertvalue { i32, i1 } %r1, i1 %cmp, 1162 ret { i32, i1 } %r2163}164 165define { i32, i1 } @dont_combine_multi_use_and(i32 %x) {166; CHECK-LABEL: dont_combine_multi_use_and:167; CHECK: // %bb.0:168; CHECK-NEXT: mov w8, #2139095040 // =0x7f800000169; CHECK-NEXT: and w0, w0, #0x7fffffff170; CHECK-NEXT: cmp w0, w8171; CHECK-NEXT: cset w1, eq172; CHECK-NEXT: ret173 %and = and i32 %x, u0x7fffffff174 %cmp = icmp eq i32 %and, u0x7f800000175 %r1 = insertvalue { i32, i1 } poison, i32 %and, 0176 %r2 = insertvalue { i32, i1 } %r1, i1 %cmp, 1177 ret { i32, i1 } %r2178}179