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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4; These test cases are inspired by C++2a std::midpoint().5; See https://bugs.llvm.org/show_bug.cgi?id=409656 7; ---------------------------------------------------------------------------- ;8; 32-bit width9; ---------------------------------------------------------------------------- ;10 11; Values come from regs12 13define i32 @scalar_i32_signed_reg_reg(i32 %a1, i32 %a2) nounwind {14; CHECK-LABEL: scalar_i32_signed_reg_reg:15; CHECK: // %bb.0:16; CHECK-NEXT: subs w9, w0, w117; CHECK-NEXT: mov w8, #-1 // =0xffffffff18; CHECK-NEXT: cneg w9, w9, le19; CHECK-NEXT: cneg w8, w8, le20; CHECK-NEXT: lsr w9, w9, #121; CHECK-NEXT: madd w0, w9, w8, w022; CHECK-NEXT: ret23 %t3 = icmp sgt i32 %a1, %a2 ; signed24 %t4 = select i1 %t3, i32 -1, i32 125 %t5 = select i1 %t3, i32 %a2, i32 %a126 %t6 = select i1 %t3, i32 %a1, i32 %a227 %t7 = sub i32 %t6, %t528 %t8 = lshr i32 %t7, 129 %t9 = mul nsw i32 %t8, %t4 ; signed30 %a10 = add nsw i32 %t9, %a1 ; signed31 ret i32 %a1032}33 34define i32 @scalar_i32_unsigned_reg_reg(i32 %a1, i32 %a2) nounwind {35; CHECK-LABEL: scalar_i32_unsigned_reg_reg:36; CHECK: // %bb.0:37; CHECK-NEXT: subs w9, w0, w138; CHECK-NEXT: mov w8, #-1 // =0xffffffff39; CHECK-NEXT: cneg w9, w9, ls40; CHECK-NEXT: cneg w8, w8, ls41; CHECK-NEXT: lsr w9, w9, #142; CHECK-NEXT: madd w0, w9, w8, w043; CHECK-NEXT: ret44 %t3 = icmp ugt i32 %a1, %a245 %t4 = select i1 %t3, i32 -1, i32 146 %t5 = select i1 %t3, i32 %a2, i32 %a147 %t6 = select i1 %t3, i32 %a1, i32 %a248 %t7 = sub i32 %t6, %t549 %t8 = lshr i32 %t7, 150 %t9 = mul i32 %t8, %t451 %a10 = add i32 %t9, %a152 ret i32 %a1053}54 55; Values are loaded. Only check signed case.56 57define i32 @scalar_i32_signed_mem_reg(ptr %a1_addr, i32 %a2) nounwind {58; CHECK-LABEL: scalar_i32_signed_mem_reg:59; CHECK: // %bb.0:60; CHECK-NEXT: ldr w9, [x0]61; CHECK-NEXT: mov w8, #-1 // =0xffffffff62; CHECK-NEXT: subs w10, w9, w163; CHECK-NEXT: cneg w10, w10, le64; CHECK-NEXT: cneg w8, w8, le65; CHECK-NEXT: lsr w10, w10, #166; CHECK-NEXT: madd w0, w10, w8, w967; CHECK-NEXT: ret68 %a1 = load i32, ptr %a1_addr69 %t3 = icmp sgt i32 %a1, %a2 ; signed70 %t4 = select i1 %t3, i32 -1, i32 171 %t5 = select i1 %t3, i32 %a2, i32 %a172 %t6 = select i1 %t3, i32 %a1, i32 %a273 %t7 = sub i32 %t6, %t574 %t8 = lshr i32 %t7, 175 %t9 = mul nsw i32 %t8, %t4 ; signed76 %a10 = add nsw i32 %t9, %a1 ; signed77 ret i32 %a1078}79 80define i32 @scalar_i32_signed_reg_mem(i32 %a1, ptr %a2_addr) nounwind {81; CHECK-LABEL: scalar_i32_signed_reg_mem:82; CHECK: // %bb.0:83; CHECK-NEXT: ldr w9, [x1]84; CHECK-NEXT: mov w8, #-1 // =0xffffffff85; CHECK-NEXT: subs w9, w0, w986; CHECK-NEXT: cneg w9, w9, le87; CHECK-NEXT: cneg w8, w8, le88; CHECK-NEXT: lsr w9, w9, #189; CHECK-NEXT: madd w0, w9, w8, w090; CHECK-NEXT: ret91 %a2 = load i32, ptr %a2_addr92 %t3 = icmp sgt i32 %a1, %a2 ; signed93 %t4 = select i1 %t3, i32 -1, i32 194 %t5 = select i1 %t3, i32 %a2, i32 %a195 %t6 = select i1 %t3, i32 %a1, i32 %a296 %t7 = sub i32 %t6, %t597 %t8 = lshr i32 %t7, 198 %t9 = mul nsw i32 %t8, %t4 ; signed99 %a10 = add nsw i32 %t9, %a1 ; signed100 ret i32 %a10101}102 103define i32 @scalar_i32_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind {104; CHECK-LABEL: scalar_i32_signed_mem_mem:105; CHECK: // %bb.0:106; CHECK-NEXT: ldr w9, [x0]107; CHECK-NEXT: ldr w10, [x1]108; CHECK-NEXT: mov w8, #-1 // =0xffffffff109; CHECK-NEXT: subs w10, w9, w10110; CHECK-NEXT: cneg w10, w10, le111; CHECK-NEXT: cneg w8, w8, le112; CHECK-NEXT: lsr w10, w10, #1113; CHECK-NEXT: madd w0, w10, w8, w9114; CHECK-NEXT: ret115 %a1 = load i32, ptr %a1_addr116 %a2 = load i32, ptr %a2_addr117 %t3 = icmp sgt i32 %a1, %a2 ; signed118 %t4 = select i1 %t3, i32 -1, i32 1119 %t5 = select i1 %t3, i32 %a2, i32 %a1120 %t6 = select i1 %t3, i32 %a1, i32 %a2121 %t7 = sub i32 %t6, %t5122 %t8 = lshr i32 %t7, 1123 %t9 = mul nsw i32 %t8, %t4 ; signed124 %a10 = add nsw i32 %t9, %a1 ; signed125 ret i32 %a10126}127 128; ---------------------------------------------------------------------------- ;129; 64-bit width130; ---------------------------------------------------------------------------- ;131 132; Values come from regs133 134define i64 @scalar_i64_signed_reg_reg(i64 %a1, i64 %a2) nounwind {135; CHECK-LABEL: scalar_i64_signed_reg_reg:136; CHECK: // %bb.0:137; CHECK-NEXT: subs x9, x0, x1138; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff139; CHECK-NEXT: cneg x9, x9, le140; CHECK-NEXT: cneg x8, x8, le141; CHECK-NEXT: lsr x9, x9, #1142; CHECK-NEXT: madd x0, x9, x8, x0143; CHECK-NEXT: ret144 %t3 = icmp sgt i64 %a1, %a2 ; signed145 %t4 = select i1 %t3, i64 -1, i64 1146 %t5 = select i1 %t3, i64 %a2, i64 %a1147 %t6 = select i1 %t3, i64 %a1, i64 %a2148 %t7 = sub i64 %t6, %t5149 %t8 = lshr i64 %t7, 1150 %t9 = mul nsw i64 %t8, %t4 ; signed151 %a10 = add nsw i64 %t9, %a1 ; signed152 ret i64 %a10153}154 155define i64 @scalar_i64_unsigned_reg_reg(i64 %a1, i64 %a2) nounwind {156; CHECK-LABEL: scalar_i64_unsigned_reg_reg:157; CHECK: // %bb.0:158; CHECK-NEXT: subs x9, x0, x1159; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff160; CHECK-NEXT: cneg x9, x9, ls161; CHECK-NEXT: cneg x8, x8, ls162; CHECK-NEXT: lsr x9, x9, #1163; CHECK-NEXT: madd x0, x9, x8, x0164; CHECK-NEXT: ret165 %t3 = icmp ugt i64 %a1, %a2166 %t4 = select i1 %t3, i64 -1, i64 1167 %t5 = select i1 %t3, i64 %a2, i64 %a1168 %t6 = select i1 %t3, i64 %a1, i64 %a2169 %t7 = sub i64 %t6, %t5170 %t8 = lshr i64 %t7, 1171 %t9 = mul i64 %t8, %t4172 %a10 = add i64 %t9, %a1173 ret i64 %a10174}175 176; Values are loaded. Only check signed case.177 178define i64 @scalar_i64_signed_mem_reg(ptr %a1_addr, i64 %a2) nounwind {179; CHECK-LABEL: scalar_i64_signed_mem_reg:180; CHECK: // %bb.0:181; CHECK-NEXT: ldr x9, [x0]182; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff183; CHECK-NEXT: subs x10, x9, x1184; CHECK-NEXT: cneg x10, x10, le185; CHECK-NEXT: cneg x8, x8, le186; CHECK-NEXT: lsr x10, x10, #1187; CHECK-NEXT: madd x0, x10, x8, x9188; CHECK-NEXT: ret189 %a1 = load i64, ptr %a1_addr190 %t3 = icmp sgt i64 %a1, %a2 ; signed191 %t4 = select i1 %t3, i64 -1, i64 1192 %t5 = select i1 %t3, i64 %a2, i64 %a1193 %t6 = select i1 %t3, i64 %a1, i64 %a2194 %t7 = sub i64 %t6, %t5195 %t8 = lshr i64 %t7, 1196 %t9 = mul nsw i64 %t8, %t4 ; signed197 %a10 = add nsw i64 %t9, %a1 ; signed198 ret i64 %a10199}200 201define i64 @scalar_i64_signed_reg_mem(i64 %a1, ptr %a2_addr) nounwind {202; CHECK-LABEL: scalar_i64_signed_reg_mem:203; CHECK: // %bb.0:204; CHECK-NEXT: ldr x9, [x1]205; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff206; CHECK-NEXT: subs x9, x0, x9207; CHECK-NEXT: cneg x9, x9, le208; CHECK-NEXT: cneg x8, x8, le209; CHECK-NEXT: lsr x9, x9, #1210; CHECK-NEXT: madd x0, x9, x8, x0211; CHECK-NEXT: ret212 %a2 = load i64, ptr %a2_addr213 %t3 = icmp sgt i64 %a1, %a2 ; signed214 %t4 = select i1 %t3, i64 -1, i64 1215 %t5 = select i1 %t3, i64 %a2, i64 %a1216 %t6 = select i1 %t3, i64 %a1, i64 %a2217 %t7 = sub i64 %t6, %t5218 %t8 = lshr i64 %t7, 1219 %t9 = mul nsw i64 %t8, %t4 ; signed220 %a10 = add nsw i64 %t9, %a1 ; signed221 ret i64 %a10222}223 224define i64 @scalar_i64_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind {225; CHECK-LABEL: scalar_i64_signed_mem_mem:226; CHECK: // %bb.0:227; CHECK-NEXT: ldr x9, [x0]228; CHECK-NEXT: ldr x10, [x1]229; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff230; CHECK-NEXT: subs x10, x9, x10231; CHECK-NEXT: cneg x10, x10, le232; CHECK-NEXT: cneg x8, x8, le233; CHECK-NEXT: lsr x10, x10, #1234; CHECK-NEXT: madd x0, x10, x8, x9235; CHECK-NEXT: ret236 %a1 = load i64, ptr %a1_addr237 %a2 = load i64, ptr %a2_addr238 %t3 = icmp sgt i64 %a1, %a2 ; signed239 %t4 = select i1 %t3, i64 -1, i64 1240 %t5 = select i1 %t3, i64 %a2, i64 %a1241 %t6 = select i1 %t3, i64 %a1, i64 %a2242 %t7 = sub i64 %t6, %t5243 %t8 = lshr i64 %t7, 1244 %t9 = mul nsw i64 %t8, %t4 ; signed245 %a10 = add nsw i64 %t9, %a1 ; signed246 ret i64 %a10247}248 249; ---------------------------------------------------------------------------- ;250; 16-bit width251; ---------------------------------------------------------------------------- ;252 253; Values come from regs254 255define i16 @scalar_i16_signed_reg_reg(i16 %a1, i16 %a2) nounwind {256; CHECK-LABEL: scalar_i16_signed_reg_reg:257; CHECK: // %bb.0:258; CHECK-NEXT: sxth w9, w0259; CHECK-NEXT: mov w8, #-1 // =0xffffffff260; CHECK-NEXT: subs w9, w9, w1, sxth261; CHECK-NEXT: cneg w8, w8, le262; CHECK-NEXT: cneg w9, w9, mi263; CHECK-NEXT: lsr w9, w9, #1264; CHECK-NEXT: madd w0, w9, w8, w0265; CHECK-NEXT: ret266 %t3 = icmp sgt i16 %a1, %a2 ; signed267 %t4 = select i1 %t3, i16 -1, i16 1268 %t5 = select i1 %t3, i16 %a2, i16 %a1269 %t6 = select i1 %t3, i16 %a1, i16 %a2270 %t7 = sub i16 %t6, %t5271 %t8 = lshr i16 %t7, 1272 %t9 = mul nsw i16 %t8, %t4 ; signed273 %a10 = add nsw i16 %t9, %a1 ; signed274 ret i16 %a10275}276 277define i16 @scalar_i16_unsigned_reg_reg(i16 %a1, i16 %a2) nounwind {278; CHECK-LABEL: scalar_i16_unsigned_reg_reg:279; CHECK: // %bb.0:280; CHECK-NEXT: and w9, w0, #0xffff281; CHECK-NEXT: mov w8, #-1 // =0xffffffff282; CHECK-NEXT: subs w9, w9, w1, uxth283; CHECK-NEXT: cneg w8, w8, ls284; CHECK-NEXT: cneg w9, w9, mi285; CHECK-NEXT: lsr w9, w9, #1286; CHECK-NEXT: madd w0, w9, w8, w0287; CHECK-NEXT: ret288 %t3 = icmp ugt i16 %a1, %a2289 %t4 = select i1 %t3, i16 -1, i16 1290 %t5 = select i1 %t3, i16 %a2, i16 %a1291 %t6 = select i1 %t3, i16 %a1, i16 %a2292 %t7 = sub i16 %t6, %t5293 %t8 = lshr i16 %t7, 1294 %t9 = mul i16 %t8, %t4295 %a10 = add i16 %t9, %a1296 ret i16 %a10297}298 299; Values are loaded. Only check signed case.300 301define i16 @scalar_i16_signed_mem_reg(ptr %a1_addr, i16 %a2) nounwind {302; CHECK-LABEL: scalar_i16_signed_mem_reg:303; CHECK: // %bb.0:304; CHECK-NEXT: ldrsh w9, [x0]305; CHECK-NEXT: mov w8, #-1 // =0xffffffff306; CHECK-NEXT: subs w10, w9, w1, sxth307; CHECK-NEXT: cneg w8, w8, le308; CHECK-NEXT: cneg w10, w10, mi309; CHECK-NEXT: lsr w10, w10, #1310; CHECK-NEXT: madd w0, w10, w8, w9311; CHECK-NEXT: ret312 %a1 = load i16, ptr %a1_addr313 %t3 = icmp sgt i16 %a1, %a2 ; signed314 %t4 = select i1 %t3, i16 -1, i16 1315 %t5 = select i1 %t3, i16 %a2, i16 %a1316 %t6 = select i1 %t3, i16 %a1, i16 %a2317 %t7 = sub i16 %t6, %t5318 %t8 = lshr i16 %t7, 1319 %t9 = mul nsw i16 %t8, %t4 ; signed320 %a10 = add nsw i16 %t9, %a1 ; signed321 ret i16 %a10322}323 324define i16 @scalar_i16_signed_reg_mem(i16 %a1, ptr %a2_addr) nounwind {325; CHECK-LABEL: scalar_i16_signed_reg_mem:326; CHECK: // %bb.0:327; CHECK-NEXT: sxth w9, w0328; CHECK-NEXT: ldrsh w10, [x1]329; CHECK-NEXT: mov w8, #-1 // =0xffffffff330; CHECK-NEXT: subs w9, w9, w10331; CHECK-NEXT: cneg w9, w9, mi332; CHECK-NEXT: cneg w8, w8, le333; CHECK-NEXT: lsr w9, w9, #1334; CHECK-NEXT: madd w0, w9, w8, w0335; CHECK-NEXT: ret336 %a2 = load i16, ptr %a2_addr337 %t3 = icmp sgt i16 %a1, %a2 ; signed338 %t4 = select i1 %t3, i16 -1, i16 1339 %t5 = select i1 %t3, i16 %a2, i16 %a1340 %t6 = select i1 %t3, i16 %a1, i16 %a2341 %t7 = sub i16 %t6, %t5342 %t8 = lshr i16 %t7, 1343 %t9 = mul nsw i16 %t8, %t4 ; signed344 %a10 = add nsw i16 %t9, %a1 ; signed345 ret i16 %a10346}347 348define i16 @scalar_i16_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind {349; CHECK-LABEL: scalar_i16_signed_mem_mem:350; CHECK: // %bb.0:351; CHECK-NEXT: ldrsh w9, [x0]352; CHECK-NEXT: ldrsh w10, [x1]353; CHECK-NEXT: mov w8, #-1 // =0xffffffff354; CHECK-NEXT: subs w10, w9, w10355; CHECK-NEXT: cneg w10, w10, mi356; CHECK-NEXT: cneg w8, w8, le357; CHECK-NEXT: lsr w10, w10, #1358; CHECK-NEXT: madd w0, w10, w8, w9359; CHECK-NEXT: ret360 %a1 = load i16, ptr %a1_addr361 %a2 = load i16, ptr %a2_addr362 %t3 = icmp sgt i16 %a1, %a2 ; signed363 %t4 = select i1 %t3, i16 -1, i16 1364 %t5 = select i1 %t3, i16 %a2, i16 %a1365 %t6 = select i1 %t3, i16 %a1, i16 %a2366 %t7 = sub i16 %t6, %t5367 %t8 = lshr i16 %t7, 1368 %t9 = mul nsw i16 %t8, %t4 ; signed369 %a10 = add nsw i16 %t9, %a1 ; signed370 ret i16 %a10371}372 373; ---------------------------------------------------------------------------- ;374; 8-bit width375; ---------------------------------------------------------------------------- ;376 377; Values come from regs378 379define i8 @scalar_i8_signed_reg_reg(i8 %a1, i8 %a2) nounwind {380; CHECK-LABEL: scalar_i8_signed_reg_reg:381; CHECK: // %bb.0:382; CHECK-NEXT: sxtb w9, w0383; CHECK-NEXT: mov w8, #-1 // =0xffffffff384; CHECK-NEXT: subs w9, w9, w1, sxtb385; CHECK-NEXT: cneg w8, w8, le386; CHECK-NEXT: cneg w9, w9, mi387; CHECK-NEXT: lsr w9, w9, #1388; CHECK-NEXT: madd w0, w9, w8, w0389; CHECK-NEXT: ret390 %t3 = icmp sgt i8 %a1, %a2 ; signed391 %t4 = select i1 %t3, i8 -1, i8 1392 %t5 = select i1 %t3, i8 %a2, i8 %a1393 %t6 = select i1 %t3, i8 %a1, i8 %a2394 %t7 = sub i8 %t6, %t5395 %t8 = lshr i8 %t7, 1396 %t9 = mul nsw i8 %t8, %t4 ; signed397 %a10 = add nsw i8 %t9, %a1 ; signed398 ret i8 %a10399}400 401define i8 @scalar_i8_unsigned_reg_reg(i8 %a1, i8 %a2) nounwind {402; CHECK-LABEL: scalar_i8_unsigned_reg_reg:403; CHECK: // %bb.0:404; CHECK-NEXT: and w9, w0, #0xff405; CHECK-NEXT: mov w8, #-1 // =0xffffffff406; CHECK-NEXT: subs w9, w9, w1, uxtb407; CHECK-NEXT: cneg w8, w8, ls408; CHECK-NEXT: cneg w9, w9, mi409; CHECK-NEXT: lsr w9, w9, #1410; CHECK-NEXT: madd w0, w9, w8, w0411; CHECK-NEXT: ret412 %t3 = icmp ugt i8 %a1, %a2413 %t4 = select i1 %t3, i8 -1, i8 1414 %t5 = select i1 %t3, i8 %a2, i8 %a1415 %t6 = select i1 %t3, i8 %a1, i8 %a2416 %t7 = sub i8 %t6, %t5417 %t8 = lshr i8 %t7, 1418 %t9 = mul i8 %t8, %t4419 %a10 = add i8 %t9, %a1420 ret i8 %a10421}422 423; Values are loaded. Only check signed case.424 425define i8 @scalar_i8_signed_mem_reg(ptr %a1_addr, i8 %a2) nounwind {426; CHECK-LABEL: scalar_i8_signed_mem_reg:427; CHECK: // %bb.0:428; CHECK-NEXT: ldrsb w9, [x0]429; CHECK-NEXT: mov w8, #-1 // =0xffffffff430; CHECK-NEXT: subs w10, w9, w1, sxtb431; CHECK-NEXT: cneg w8, w8, le432; CHECK-NEXT: cneg w10, w10, mi433; CHECK-NEXT: lsr w10, w10, #1434; CHECK-NEXT: madd w0, w10, w8, w9435; CHECK-NEXT: ret436 %a1 = load i8, ptr %a1_addr437 %t3 = icmp sgt i8 %a1, %a2 ; signed438 %t4 = select i1 %t3, i8 -1, i8 1439 %t5 = select i1 %t3, i8 %a2, i8 %a1440 %t6 = select i1 %t3, i8 %a1, i8 %a2441 %t7 = sub i8 %t6, %t5442 %t8 = lshr i8 %t7, 1443 %t9 = mul nsw i8 %t8, %t4 ; signed444 %a10 = add nsw i8 %t9, %a1 ; signed445 ret i8 %a10446}447 448define i8 @scalar_i8_signed_reg_mem(i8 %a1, ptr %a2_addr) nounwind {449; CHECK-LABEL: scalar_i8_signed_reg_mem:450; CHECK: // %bb.0:451; CHECK-NEXT: sxtb w9, w0452; CHECK-NEXT: ldrsb w10, [x1]453; CHECK-NEXT: mov w8, #-1 // =0xffffffff454; CHECK-NEXT: subs w9, w9, w10455; CHECK-NEXT: cneg w9, w9, mi456; CHECK-NEXT: cneg w8, w8, le457; CHECK-NEXT: lsr w9, w9, #1458; CHECK-NEXT: madd w0, w9, w8, w0459; CHECK-NEXT: ret460 %a2 = load i8, ptr %a2_addr461 %t3 = icmp sgt i8 %a1, %a2 ; signed462 %t4 = select i1 %t3, i8 -1, i8 1463 %t5 = select i1 %t3, i8 %a2, i8 %a1464 %t6 = select i1 %t3, i8 %a1, i8 %a2465 %t7 = sub i8 %t6, %t5466 %t8 = lshr i8 %t7, 1467 %t9 = mul nsw i8 %t8, %t4 ; signed468 %a10 = add nsw i8 %t9, %a1 ; signed469 ret i8 %a10470}471 472define i8 @scalar_i8_signed_mem_mem(ptr %a1_addr, ptr %a2_addr) nounwind {473; CHECK-LABEL: scalar_i8_signed_mem_mem:474; CHECK: // %bb.0:475; CHECK-NEXT: ldrsb w9, [x0]476; CHECK-NEXT: ldrsb w10, [x1]477; CHECK-NEXT: mov w8, #-1 // =0xffffffff478; CHECK-NEXT: subs w10, w9, w10479; CHECK-NEXT: cneg w10, w10, mi480; CHECK-NEXT: cneg w8, w8, le481; CHECK-NEXT: lsr w10, w10, #1482; CHECK-NEXT: madd w0, w10, w8, w9483; CHECK-NEXT: ret484 %a1 = load i8, ptr %a1_addr485 %a2 = load i8, ptr %a2_addr486 %t3 = icmp sgt i8 %a1, %a2 ; signed487 %t4 = select i1 %t3, i8 -1, i8 1488 %t5 = select i1 %t3, i8 %a2, i8 %a1489 %t6 = select i1 %t3, i8 %a1, i8 %a2490 %t7 = sub i8 %t6, %t5491 %t8 = lshr i8 %t7, 1492 %t9 = mul nsw i8 %t8, %t4 ; signed493 %a10 = add nsw i8 %t9, %a1 ; signed494 ret i8 %a10495}496