121 lines · plain
1; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=fuse-address | FileCheck %s2; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a65 | FileCheck %s3; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s4; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s5; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s6; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=ampere1 | FileCheck %s7; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=ampere1a | FileCheck %s8; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=ampere1b | FileCheck %s9 10target triple = "aarch64-unknown"11 12@var_8bit = dso_local global i8 013@var_16bit = dso_local global i16 014@var_32bit = dso_local global i32 015@var_64bit = dso_local global i64 016@var_128bit = dso_local global i128 017@var_half = dso_local global half 0.018@var_float = dso_local global float 0.019@var_double = dso_local global double 0.020@var_double2 = dso_local global <2 x double> <double 0.0, double 0.0>21 22define dso_local void @ldst_8bit() {23 %val8 = load volatile i8, ptr @var_8bit24 %ext = zext i8 %val8 to i6425 %add = add i64 %ext, 126 %val16 = trunc i64 %add to i1627 store volatile i16 %val16, ptr @var_16bit28 ret void29 30; CHECK-LABEL: ldst_8bit:31; CHECK: adrp [[RB:x[0-9]+]], var_8bit32; CHECK-NEXT: ldrb {{w[0-9]+}}, [[[RB]], {{#?}}:lo12:var_8bit]33; CHECK: adrp [[RH:x[0-9]+]], var_16bit34; CHECK-NEXT: strh {{w[0-9]+}}, [[[RH]], {{#?}}:lo12:var_16bit]35}36 37define dso_local void @ldst_16bit() {38 %val16 = load volatile i16, ptr @var_16bit39 %ext = zext i16 %val16 to i6440 %add = add i64 %ext, 141 %val32 = trunc i64 %add to i3242 store volatile i32 %val32, ptr @var_32bit43 ret void44 45; CHECK-LABEL: ldst_16bit:46; CHECK: adrp [[RH:x[0-9]+]], var_16bit47; CHECK-NEXT: ldrh {{w[0-9]+}}, [[[RH]], {{#?}}:lo12:var_16bit]48; CHECK: adrp [[RW:x[0-9]+]], var_32bit49; CHECK-NEXT: str {{w[0-9]+}}, [[[RW]], {{#?}}:lo12:var_32bit]50}51 52define dso_local void @ldst_32bit() {53 %val32 = load volatile i32, ptr @var_32bit54 %ext = zext i32 %val32 to i6455 %val64 = add i64 %ext, 156 store volatile i64 %val64, ptr @var_64bit57 ret void58 59; CHECK-LABEL: ldst_32bit:60; CHECK: adrp [[RW:x[0-9]+]], var_32bit61; CHECK-NEXT: ldr {{w[0-9]+}}, [[[RW]], {{#?}}:lo12:var_32bit]62; CHECK: adrp [[RL:x[0-9]+]], var_64bit63; CHECK-NEXT: str {{x[0-9]+}}, [[[RL]], {{#?}}:lo12:var_64bit]64}65 66define dso_local void @ldst_64bit() {67 %val64 = load volatile i64, ptr @var_64bit68 %ext = zext i64 %val64 to i12869 %val128 = add i128 %ext, 170 store volatile i128 %val128, ptr @var_128bit71 ret void72 73; CHECK-LABEL: ldst_64bit:74; CHECK: adrp [[RL:x[0-9]+]], var_64bit75; CHECK-NEXT: ldr {{x[0-9]+}}, [[[RL]], {{#?}}:lo12:var_64bit]76; CHECK: adrp [[RQ:x[0-9]+]], var_128bit77; CHECK-NEXT: add {{x[0-9]+}}, [[RQ]], {{#?}}:lo12:var_128bit78}79 80define dso_local void @ldst_half() {81 %valh = load volatile half, ptr @var_half82 %valf = fpext half %valh to float83 store volatile float %valf, ptr @var_float84 ret void85 86; CHECK-LABEL: ldst_half:87; CHECK: adrp [[RH:x[0-9]+]], var_half88; CHECK-NEXT: ldr {{h[0-9]+}}, [[[RH]], {{#?}}:lo12:var_half]89; CHECK: adrp [[RF:x[0-9]+]], var_float90; CHECK-NEXT: str {{s[0-9]+}}, [[[RF]], {{#?}}:lo12:var_float]91}92 93define dso_local void @ldst_float() {94 %valf = load volatile float, ptr @var_float95 %vald = fpext float %valf to double96 store volatile double %vald, ptr @var_double97 ret void98 99; CHECK-LABEL: ldst_float:100; CHECK: adrp [[RF:x[0-9]+]], var_float101; CHECK-NEXT: ldr {{s[0-9]+}}, [[[RF]], {{#?}}:lo12:var_float]102; CHECK: adrp [[RD:x[0-9]+]], var_double103; CHECK-NEXT: str {{d[0-9]+}}, [[[RD]], {{#?}}:lo12:var_double]104}105 106define dso_local void @ldst_double() {107 %valf = load volatile float, ptr @var_float108 %vale = fpext float %valf to double109 %vald = load volatile double, ptr @var_double110 %vald1 = insertelement <2 x double> undef, double %vald, i32 0111 %vald2 = insertelement <2 x double> %vald1, double %vale, i32 1112 store volatile <2 x double> %vald2, ptr @var_double2113 ret void114 115; CHECK-LABEL: ldst_double:116; CHECK: adrp [[RD:x[0-9]+]], var_double117; CHECK-NEXT: ldr {{d[0-9]+}}, [[[RD]], {{#?}}:lo12:var_double]118; CHECK: adrp [[RQ:x[0-9]+]], var_double2119; CHECK-NEXT: str {{q[0-9]+}}, [[[RQ]], {{#?}}:lo12:var_double2]120}121