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1# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -run-pass=machine-scheduler -misched-print-dags | FileCheck %s2# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -passes=machine-scheduler -misched-print-dags | FileCheck %s3# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=exynos-m4 -run-pass=machine-scheduler -misched-print-dags | FileCheck %s4# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=exynos-m4 -passes=machine-scheduler -misched-print-dags | FileCheck %s5# REQUIRES: asserts6 7---8name: arith9body: |10 bb.0.entry:11 %0:gpr32 = SUBWrr undef $w0, undef $w112 %1:gpr32 = ADDWrr undef $w1, undef $w213 %2:gpr32 = SUBWrs %0, undef $w2, 014 %3:gpr32 = ADDWrs %1, undef $w3, 015 16 ; CHECK: SU(0): %0:gpr32 = SUBWrr undef $w0, undef $w117 ; CHECK: Successors:18 ; CHECK: SU(2): Ord Latency=0 Cluster19 ; CHECK: SU(1): %1:gpr32 = ADDWrr undef $w1, undef $w220 ; CHECK: Successors:21 ; CHECK: SU(3): Ord Latency=0 Cluster22 ; CHECK: SU(2): dead %2:gpr32 = SUBWrs %0:gpr32, undef $w2, 023 ; CHECK: Predecessors:24 ; CHECK: SU(0): Ord Latency=0 Cluster25 ; CHECK: SU(3): dead %3:gpr32 = ADDWrs %1:gpr32, undef $w3, 026 ; CHECK: Predecessors:27 ; CHECK: SU(1): Ord Latency=0 Cluster28...29---30name: compare31body: |32 bb.0.entry:33 %0:gpr64 = ADDXrr undef $x0, undef $x134 %1:gpr64 = SUBXrs undef $x1, undef $x2, 035 %2:gpr64 = ADDSXrr %0, undef $x3, implicit-def $nzcv36 %3:gpr64 = SUBSXrs %1, undef $x4, 0, implicit-def $nzcv37 38 ; CHECK: SU(0): %0:gpr64 = ADDXrr undef $x0, undef $x139 ; CHECK: Successors:40 ; CHECK: SU(2): Ord Latency=0 Cluster41 ; CHECK: SU(1): %1:gpr64 = SUBXrs undef $x1, undef $x2, 042 ; CHECK: Successors:43 ; CHECK: SU(3): Ord Latency=0 Cluster44 ; CHECK: SU(2): dead %2:gpr64 = ADDSXrr %0:gpr64, undef $x3, implicit-def $nzcv45 ; CHECK: Predecessors:46 ; CHECK: SU(0): Ord Latency=0 Cluster47 ; CHECK: SU(3): dead %3:gpr64 = SUBSXrs %1:gpr64, undef $x4, 0, implicit-def $nzcv48 ; CHECK: Predecessors:49 ; CHECK: SU(1): Ord Latency=0 Cluster50...51---52name: logic53body: |54 bb.0.entry:55 %0:gpr32 = ADDWrr undef $w0, undef $w156 %1:gpr64 = SUBXrs undef $x1, undef $x2, 057 %3:gpr32 = ANDWrs %0, undef $w3, 058 %4:gpr64 = ORRXrr %1, undef $x459 60 ; CHECK: SU(0): %0:gpr32 = ADDWrr undef $w0, undef $w161 ; CHECK: Successors:62 ; CHECK: SU(2): Ord Latency=0 Cluster63 ; CHECK: SU(1): %1:gpr64 = SUBXrs undef $x1, undef $x2, 064 ; CHECK: Successors:65 ; CHECK: SU(3): Ord Latency=0 Cluster66 ; CHECK: SU(2): dead %2:gpr32 = ANDWrs %0:gpr32, undef $w3, 067 ; CHECK: Predecessors:68 ; CHECK: SU(0): Ord Latency=0 Cluster69 ; CHECK: SU(3): dead %3:gpr64 = ORRXrr %1:gpr64, undef $x470 ; CHECK: Predecessors:71 ; CHECK: SU(1): Ord Latency=0 Cluster72...73---74name: nope75body: |76 bb.0.entry:77 ; Shifted register.78 %0:gpr32 = SUBWrr undef $w0, undef $w179 %1:gpr32 = SUBWrs %0, undef $w2, 180 ; CHECK: SU(0): %0:gpr32 = SUBWrr undef $w0, undef $w181 ; CHECK: Successors:82 ; CHECK-NOT: SU(1): Ord Latency=0 Cluster83 ; CHECK: SU(1): dead %1:gpr32 = SUBWrs %0:gpr32, undef $w2, 184 85 ; Multiple successors.86 %2:gpr64 = ADDXrr undef $x0, undef $x187 %3:gpr32 = EXTRACT_SUBREG %2, %subreg.sub_3288 %4:gpr32 = ANDWrs %3, undef $w2, 089 %5:gpr64 = ADDSXrr %2, undef $x3, implicit-def $nzcv90 ; CHECK: SU(2): %2:gpr64 = ADDXrr undef $x0, undef $x191 ; CHECK: Successors:92 ; CHECK-NOT: SU(3): Ord Latency=0 Cluster93 ; CHECK: SU(5): Ord Latency=0 Cluster94 ; CHECK: SU(3): %3:gpr32 = EXTRACT_SUBREG %2:gpr64, %subreg.sub_3295 ; CHECK: SU(5): dead %5:gpr64 = ADDSXrr %2:gpr64, undef $x3, implicit-def $nzcv96 97 ; Different register sizes.98 %6:gpr32 = SUBWrr undef $w0, undef $w199 %7:gpr64 = ADDXrr undef $x1, undef $x2100 %8:gpr64 = SUBXrr %7, undef $x3101 %9:gpr32 = ADDWrr %6, undef $w4102 ; CHECK: SU(6): %6:gpr32 = SUBWrr undef $w0, undef $w1103 ; CHECK: Successors:104 ; CHECK-NOT: SU(8): Ord Latency=0 Cluster105 ; CHECK: SU(7): %7:gpr64 = ADDXrr undef $x1, undef $x2106 ; CHECK: Successors:107 ; CHECK-NOT: SU(9): Ord Latency=0 Cluster108 ; CHECK: SU(8): dead %8:gpr64 = SUBXrr %7:gpr64, undef $x3109 ; CHECK: Predecessors:110 ; CHECK: SU(7): Ord Latency=0 Cluster111 ; CHECK: SU(9): dead %9:gpr32 = ADDWrr %6:gpr32, undef $w4112 ; CHECK: Predecessors:113 ; CHECK: SU(6): Ord Latency=0 Cluster114...115