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1; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=fuse-csel -debug-only=machine-scheduler 2>&1 | FileCheck %s2; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 -debug-only=machine-scheduler 2>&1 | FileCheck %s3; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 -debug-only=machine-scheduler 2>&1 | FileCheck %s4; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 -debug-only=machine-scheduler 2>&1 | FileCheck %s5; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a78 -debug-only=machine-scheduler 2>&1 | FileCheck %s6; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a710 -debug-only=machine-scheduler 2>&1 | FileCheck %s7; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a715 -debug-only=machine-scheduler 2>&1 | FileCheck %s8; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a720 -debug-only=machine-scheduler 2>&1 | FileCheck %s9; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a725 -debug-only=machine-scheduler 2>&1 | FileCheck %s10; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-x4 -debug-only=machine-scheduler 2>&1 | FileCheck %s11; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-x925 -debug-only=machine-scheduler 2>&1 | FileCheck %s12; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n2 -debug-only=machine-scheduler 2>&1 | FileCheck %s13; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n3 -debug-only=machine-scheduler 2>&1 | FileCheck %s14; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v1 -debug-only=machine-scheduler 2>&1 | FileCheck %s15; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v2 -debug-only=machine-scheduler 2>&1 | FileCheck %s16; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v3 -debug-only=machine-scheduler 2>&1 | FileCheck %s17; REQUIRES: asserts18 19; Check that the scheduling model has an edge between the SUBS and the CSEL.20; CHECK-LABEL: test_sub_cselw:%bb.021; CHECK: SU(2): %3:gpr32common = ADDWri %1:gpr32common, 7, 022; CHECK: SU(3): dead $wzr = SUBSWri %0:gpr32common, 13, 0, implicit-def $nzcv23; CHECK: Successors:24; CHECK: SU(4): Ord Latency=0 Cluster25; CHECK: SU(4): %5:gpr32 = CSELWr %0:gpr32common, %3:gpr32common, 0, implicit killed $nzcv26; CHECK: Predecessors:27; CHECK: SU(3): Ord Latency=0 Cluster28; CHECK: SU(5): $w0 = COPY %5:gpr3229 30 31; CHECK-LABEL: test_sub_cselx:%bb.032; CHECK: SU(2): %3:gpr64common = ADDXri %1:gpr64common, 7, 033; CHECK: SU(3): dead $xzr = SUBSXri %0:gpr64common, 13, 0, implicit-def $nzcv34; CHECK: Successors:35; CHECK: SU(4): Ord Latency=0 Cluster36; CHECK: SU(4): %5:gpr64 = CSELXr %0:gpr64common, %3:gpr64common, 0, implicit killed $nzcv37; CHECK: Predecessors:38; CHECK: SU(3): Ord Latency=0 Cluster39; CHECK: SU(5): $x0 = COPY %5:gpr6440 41define i32 @test_sub_cselw(i32 %a0, i32 %a1, i32 %a2) {42entry:43 %v0 = sub i32 %a0, 1344 %cond = icmp eq i32 %v0, 045 %v1 = add i32 %a1, 746 %v2 = select i1 %cond, i32 %a0, i32 %v147 ret i32 %v248 49; CHECK-LABEL: test_sub_cselw:50; CHECK: cmp {{w[0-9]}}, #1351; CHECK-NEXT: csel {{w[0-9]}}52}53 54define i64 @test_sub_cselx(i64 %a0, i64 %a1, i64 %a2) {55entry:56 %v0 = sub i64 %a0, 1357 %cond = icmp eq i64 %v0, 058 %v1 = add i64 %a1, 759 %v2 = select i1 %cond, i64 %a0, i64 %v160 ret i64 %v261 62; CHECK-LABEL: test_sub_cselx:63; CHECK: cmp {{x[0-9]}}, #1364; CHECK-NEXT: csel {{x[0-9]}}65}66