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1# RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s2# RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -passes=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s3# REQUIRES: asserts4 5# CHECK-LABEL: ********** MI Scheduling **********6# CHECK: SU(0): %0:fpr128 = COPY $q17# CHECK-NEXT: # preds left : 08# CHECK-NEXT: # succs left : 19# CHECK-NEXT: # rdefs left : 010# CHECK-NEXT: Latency : 211# CHECK-NEXT: Depth : 012# CHECK-NEXT: Height : 1213# CHECK-NEXT: Successors:14# CHECK-NEXT: SU(1): Data Latency=2 Reg=%015# CHECK-NEXT: Single Issue : false;16# CHECK-NEXT: SU(1): %1:fpr32 = FMINVv4i32v %0:fpr128, implicit $fpcr17# CHECK-NEXT: # preds left : 118# CHECK-NEXT: # succs left : 119# CHECK-NEXT: # rdefs left : 020# CHECK-NEXT: Latency : 821# CHECK-NEXT: Depth : 222# CHECK-NEXT: Height : 1023# CHECK-NEXT: Predecessors:24# CHECK-NEXT: SU(0): Data Latency=2 Reg=%025# CHECK-NEXT: Successors:26# CHECK-NEXT: SU(2): Data Latency=8 Reg=%127# CHECK-NEXT: Single Issue : false;28 29name: test_qform_virtreg30tracksRegLiveness: true31body: |32 bb.0:33 liveins: $s0, $q134 %0:fpr128 = COPY $q135 %1:fpr32 = FMINVv4i32v %0:fpr128, implicit $fpcr36 $s0 = COPY %137 RET_ReallyLR implicit $s038 39