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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+slow-misaligned-128store -enable-misched -verify-misched -o - | FileCheck %s3 4; Tests to check that the scheduler dependencies derived from alias analysis are5; correct when we have loads that have been split up so that they can later be6; merged into STP.7 8; Now that overwritten stores are elided in SelectionDAG, dependencies9; are resolved and removed before MISCHED. Check that we have10; equivalent pair of stp calls as a baseline.11 12; CHECK-LABEL: test_splat13; CHECK: ldr [[REG:w[0-9]+]], [x2]14; CHECK-DAG: stp w0, [[REG]], [x2, #12]15; CHECK-DAG: stp [[REG]], w1, [x2, #4]16define void @test_splat(i32 %x, i32 %y, ptr %p) {17entry:18 %val = load i32, ptr %p, align 419 %0 = getelementptr inbounds i32, ptr %p, i64 120 %1 = getelementptr inbounds i32, ptr %p, i64 221 %2 = getelementptr inbounds i32, ptr %p, i64 322 %vec0 = insertelement <4 x i32> undef, i32 %val, i32 023 %vec1 = insertelement <4 x i32> %vec0, i32 %val, i32 124 %vec2 = insertelement <4 x i32> %vec1, i32 %val, i32 225 %vec3 = insertelement <4 x i32> %vec2, i32 %val, i32 326 store <4 x i32> %vec3, ptr %0, align 427 store i32 %x, ptr %2, align 428 store i32 %y, ptr %1, align 429 ret void30}31 32declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1)33%struct.tree_common = type { ptr, ptr, i32 }34 35; CHECK-LABEL: test_zero36; CHECK-DAG: stp x2, xzr, [x0, #8]37; CHECK-DAG: str w1, [x0, #16]38; CHECK-DAG: str xzr, [x0]39 40define void @test_zero(ptr %t, i32 %code, ptr %type) {41entry:42 tail call void @llvm.memset.p0.i64(ptr align 8 %t, i8 0, i64 24, i1 false)43 %code1 = getelementptr inbounds %struct.tree_common, ptr %t, i64 0, i32 244 store i32 %code, ptr %code1, align 845 %type2 = getelementptr inbounds %struct.tree_common, ptr %t, i64 0, i32 146 store ptr %type, ptr %type2, align 847 ret void48}49