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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s3 4define <4 x i16> @test_mla0(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {5; CHECK-LABEL: test_mla0:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: umull v2.8h, v2.8b, v3.8b8; CHECK-NEXT: umlal v2.8h, v0.8b, v1.8b9; CHECK-NEXT: fmov d0, d210; CHECK-NEXT: ret11entry:12 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %a, <8 x i8> %b)13 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %c, <8 x i8> %d)14 %add.i = add <8 x i16> %vmull.i.i, %vmull.i15 %shuffle.i = shufflevector <8 x i16> %add.i, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>16 ret <4 x i16> %shuffle.i17}18 19 20define <4 x i16> @test_mla1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {21; CHECK-LABEL: test_mla1:22; CHECK: // %bb.0: // %entry23; CHECK-NEXT: smull v2.8h, v2.8b, v3.8b24; CHECK-NEXT: smlal v2.8h, v0.8b, v1.8b25; CHECK-NEXT: fmov d0, d226; CHECK-NEXT: ret27entry:28 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %a, <8 x i8> %b)29 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %c, <8 x i8> %d)30 %add.i = add <8 x i16> %vmull.i.i, %vmull.i31 %shuffle.i = shufflevector <8 x i16> %add.i, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>32 ret <4 x i16> %shuffle.i33}34 35 36define <2 x i32> @test_mla2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {37; CHECK-LABEL: test_mla2:38; CHECK: // %bb.0: // %entry39; CHECK-NEXT: umull v2.4s, v2.4h, v3.4h40; CHECK-NEXT: umlal v2.4s, v0.4h, v1.4h41; CHECK-NEXT: fmov d0, d242; CHECK-NEXT: ret43entry:44 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %b)45 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %c, <4 x i16> %d)46 %add.i = add <4 x i32> %vmull2.i.i, %vmull2.i47 %shuffle.i = shufflevector <4 x i32> %add.i, <4 x i32> undef, <2 x i32> <i32 0, i32 1>48 ret <2 x i32> %shuffle.i49}50 51 52define <2 x i32> @test_mla3(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {53; CHECK-LABEL: test_mla3:54; CHECK: // %bb.0: // %entry55; CHECK-NEXT: smull v2.4s, v2.4h, v3.4h56; CHECK-NEXT: smlal v2.4s, v0.4h, v1.4h57; CHECK-NEXT: fmov d0, d258; CHECK-NEXT: ret59entry:60 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %b)61 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %c, <4 x i16> %d)62 %add.i = add <4 x i32> %vmull2.i.i, %vmull2.i63 %shuffle.i = shufflevector <4 x i32> %add.i, <4 x i32> undef, <2 x i32> <i32 0, i32 1>64 ret <2 x i32> %shuffle.i65}66 67 68define <1 x i64> @test_mla4(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {69; CHECK-LABEL: test_mla4:70; CHECK: // %bb.0: // %entry71; CHECK-NEXT: umull v2.2d, v2.2s, v3.2s72; CHECK-NEXT: umlal v2.2d, v0.2s, v1.2s73; CHECK-NEXT: fmov d0, d274; CHECK-NEXT: ret75entry:76 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %b)77 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %c, <2 x i32> %d)78 %add.i = add <2 x i64> %vmull2.i.i, %vmull2.i79 %shuffle.i = shufflevector <2 x i64> %add.i, <2 x i64> undef, <1 x i32> zeroinitializer80 ret <1 x i64> %shuffle.i81}82 83 84define <1 x i64> @test_mla5(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {85; CHECK-LABEL: test_mla5:86; CHECK: // %bb.0: // %entry87; CHECK-NEXT: smull v2.2d, v2.2s, v3.2s88; CHECK-NEXT: smlal v2.2d, v0.2s, v1.2s89; CHECK-NEXT: fmov d0, d290; CHECK-NEXT: ret91entry:92 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %b)93 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %c, <2 x i32> %d)94 %add.i = add <2 x i64> %vmull2.i.i, %vmull2.i95 %shuffle.i = shufflevector <2 x i64> %add.i, <2 x i64> undef, <1 x i32> zeroinitializer96 ret <1 x i64> %shuffle.i97}98 99 100define <4 x i16> @test_mls0(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {101; CHECK-LABEL: test_mls0:102; CHECK: // %bb.0: // %entry103; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b104; CHECK-NEXT: umlsl v0.8h, v2.8b, v3.8b105; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0106; CHECK-NEXT: ret107entry:108 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %a, <8 x i8> %b)109 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %c, <8 x i8> %d)110 %sub.i = sub <8 x i16> %vmull.i, %vmull.i.i111 %shuffle.i = shufflevector <8 x i16> %sub.i, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>112 ret <4 x i16> %shuffle.i113}114 115 116define <4 x i16> @test_mls1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {117; CHECK-LABEL: test_mls1:118; CHECK: // %bb.0: // %entry119; CHECK-NEXT: smull v0.8h, v0.8b, v1.8b120; CHECK-NEXT: smlsl v0.8h, v2.8b, v3.8b121; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0122; CHECK-NEXT: ret123entry:124 %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %a, <8 x i8> %b)125 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %c, <8 x i8> %d)126 %sub.i = sub <8 x i16> %vmull.i, %vmull.i.i127 %shuffle.i = shufflevector <8 x i16> %sub.i, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>128 ret <4 x i16> %shuffle.i129}130 131 132define <2 x i32> @test_mls2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {133; CHECK-LABEL: test_mls2:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h136; CHECK-NEXT: umlsl v0.4s, v2.4h, v3.4h137; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0138; CHECK-NEXT: ret139entry:140 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %b)141 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %c, <4 x i16> %d)142 %sub.i = sub <4 x i32> %vmull2.i, %vmull2.i.i143 %shuffle.i = shufflevector <4 x i32> %sub.i, <4 x i32> undef, <2 x i32> <i32 0, i32 1>144 ret <2 x i32> %shuffle.i145}146 147 148define <2 x i32> @test_mls3(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {149; CHECK-LABEL: test_mls3:150; CHECK: // %bb.0: // %entry151; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h152; CHECK-NEXT: smlsl v0.4s, v2.4h, v3.4h153; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0154; CHECK-NEXT: ret155entry:156 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %b)157 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %c, <4 x i16> %d)158 %sub.i = sub <4 x i32> %vmull2.i, %vmull2.i.i159 %shuffle.i = shufflevector <4 x i32> %sub.i, <4 x i32> undef, <2 x i32> <i32 0, i32 1>160 ret <2 x i32> %shuffle.i161}162 163 164define <1 x i64> @test_mls4(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {165; CHECK-LABEL: test_mls4:166; CHECK: // %bb.0: // %entry167; CHECK-NEXT: umull v0.2d, v0.2s, v1.2s168; CHECK-NEXT: umlsl v0.2d, v2.2s, v3.2s169; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0170; CHECK-NEXT: ret171entry:172 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %b)173 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %c, <2 x i32> %d)174 %sub.i = sub <2 x i64> %vmull2.i, %vmull2.i.i175 %shuffle.i = shufflevector <2 x i64> %sub.i, <2 x i64> undef, <1 x i32> zeroinitializer176 ret <1 x i64> %shuffle.i177}178 179 180define <1 x i64> @test_mls5(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {181; CHECK-LABEL: test_mls5:182; CHECK: // %bb.0: // %entry183; CHECK-NEXT: smull v0.2d, v0.2s, v1.2s184; CHECK-NEXT: smlsl v0.2d, v2.2s, v3.2s185; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0186; CHECK-NEXT: ret187entry:188 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %b)189 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %c, <2 x i32> %d)190 %sub.i = sub <2 x i64> %vmull2.i, %vmull2.i.i191 %shuffle.i = shufflevector <2 x i64> %sub.i, <2 x i64> undef, <1 x i32> zeroinitializer192 ret <1 x i64> %shuffle.i193}194 195declare <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8>, <8 x i8>)196 197declare <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8>, <8 x i8>)198 199declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>)200 201declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>)202 203declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)204 205declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)206