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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -mtriple=aarch64 -verify-machineinstrs -run-pass=aarch64-expand-pseudo -run-pass=aarch64-ldst-opt -debug-only=aarch64-ldst-opt %s -o - | FileCheck %s3# REQUIRES: asserts4---5name: test_fold_repeating_constant_load6tracksRegLiveness: true7body: |8 bb.0:9 liveins: $x010 ; CHECK-LABEL: name: test_fold_repeating_constant_load11 ; CHECK: liveins: $x012 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: renamable $x0 = MOVZXi 49370, 014 ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 320, 1615 ; CHECK-NEXT: renamable $x0 = ORRXrs $x0, $x0, 3216 ; CHECK-NEXT: RET undef $lr, implicit $x017 renamable $x0 = MOVi64imm 9028403510383433018 RET_ReallyLR implicit $x019...20---21name: test_fold_repeating_constant_load_neg22tracksRegLiveness: true23body: |24 bb.0:25 liveins: $x026 ; CHECK-LABEL: name: test_fold_repeating_constant_load_neg27 ; CHECK: liveins: $x028 ; CHECK-NEXT: {{ $}}29 ; CHECK-NEXT: renamable $x0 = MOVZXi 320, 030 ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 49370, 1631 ; CHECK-NEXT: renamable $x0 = ORRXrs $x0, $x0, 3232 ; CHECK-NEXT: RET undef $lr, implicit $x033 renamable $x0 = MOVi64imm -455032309587941753634 RET_ReallyLR implicit $x035