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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 %s -o - -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <1 x i64> @v1i64(<1 x i64> %a) {6; CHECK-SD-LABEL: v1i64:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: cmlt v0.2s, v0.2s, #09; CHECK-SD-NEXT: ret10;11; CHECK-GI-LABEL: v1i64:12; CHECK-GI: // %bb.0:13; CHECK-GI-NEXT: fmov x8, d014; CHECK-GI-NEXT: lsr x8, x8, #3115; CHECK-GI-NEXT: and x8, x8, #0x10000000116; CHECK-GI-NEXT: lsl x9, x8, #3217; CHECK-GI-NEXT: sub x8, x9, x818; CHECK-GI-NEXT: fmov d0, x819; CHECK-GI-NEXT: ret20 %b = lshr <1 x i64> %a, <i64 31>21 %c = and <1 x i64> %b, <i64 4294967297>22 %d = mul nuw <1 x i64> %c, <i64 4294967295>23 ret <1 x i64> %d24}25 26define <2 x i64> @v2i64(<2 x i64> %a) {27; CHECK-LABEL: v2i64:28; CHECK: // %bb.0:29; CHECK-NEXT: cmlt v0.4s, v0.4s, #030; CHECK-NEXT: ret31 %b = lshr <2 x i64> %a, <i64 31, i64 31>32 %c = and <2 x i64> %b, <i64 4294967297, i64 4294967297>33 %d = mul nuw <2 x i64> %c, <i64 4294967295, i64 4294967295>34 ret <2 x i64> %d35}36 37define <2 x i32> @v2i32(<2 x i32> %a) {38; CHECK-LABEL: v2i32:39; CHECK: // %bb.0:40; CHECK-NEXT: cmlt v0.4h, v0.4h, #041; CHECK-NEXT: ret42 %b = lshr <2 x i32> %a, <i32 15, i32 15>43 %c = and <2 x i32> %b, <i32 65537, i32 65537>44 %d = mul nuw <2 x i32> %c, <i32 65535, i32 65535>45 ret <2 x i32> %d46}47 48define <4 x i32> @v4i32(<4 x i32> %a) {49; CHECK-LABEL: v4i32:50; CHECK: // %bb.0:51; CHECK-NEXT: cmlt v0.8h, v0.8h, #052; CHECK-NEXT: ret53 %b = lshr <4 x i32> %a, <i32 15, i32 15, i32 15, i32 15>54 %c = and <4 x i32> %b, <i32 65537, i32 65537, i32 65537, i32 65537>55 %d = mul nuw <4 x i32> %c, <i32 65535, i32 65535, i32 65535, i32 65535>56 ret <4 x i32> %d57}58 59define <8 x i32> @v8i32(<8 x i32> %a) {60; CHECK-LABEL: v8i32:61; CHECK: // %bb.0:62; CHECK-NEXT: cmlt v0.8h, v0.8h, #063; CHECK-NEXT: cmlt v1.8h, v1.8h, #064; CHECK-NEXT: ret65 %b = lshr <8 x i32> %a, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>66 %c = and <8 x i32> %b, <i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537, i32 65537>67 %d = mul nuw <8 x i32> %c, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>68 ret <8 x i32> %d69}70 71define <4 x i16> @v4i16(<4 x i16> %a) {72; CHECK-LABEL: v4i16:73; CHECK: // %bb.0:74; CHECK-NEXT: cmlt v0.8b, v0.8b, #075; CHECK-NEXT: ret76 %b = lshr <4 x i16> %a, <i16 7, i16 7, i16 7, i16 7>77 %c = and <4 x i16> %b, <i16 257, i16 257, i16 257, i16 257>78 %d = mul nuw <4 x i16> %c, <i16 255, i16 255, i16 255, i16 255>79 ret <4 x i16> %d80}81 82define <8 x i16> @v8i16(<8 x i16> %a) {83; CHECK-LABEL: v8i16:84; CHECK: // %bb.0:85; CHECK-NEXT: cmlt v0.16b, v0.16b, #086; CHECK-NEXT: ret87 %b = lshr <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>88 %c = and <8 x i16> %b, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>89 %d = mul nuw <8 x i16> %c, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>90 ret <8 x i16> %d91}92 93define <8 x i8> @v8i8(<8 x i8> %a) {94; CHECK-LABEL: v8i8:95; CHECK: // %bb.0:96; CHECK-NEXT: movi v1.8b, #1797; CHECK-NEXT: ushr v0.8b, v0.8b, #398; CHECK-NEXT: movi v2.8b, #1599; CHECK-NEXT: and v0.8b, v0.8b, v1.8b100; CHECK-NEXT: mul v0.8b, v0.8b, v2.8b101; CHECK-NEXT: ret102 %b = lshr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>103 %c = and <8 x i8> %b, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17>104 %d = mul nuw <8 x i8> %c, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>105 ret <8 x i8> %d106}107 108define <16 x i8> @v16i8(<16 x i8> %a) {109; CHECK-LABEL: v16i8:110; CHECK: // %bb.0:111; CHECK-NEXT: movi v1.16b, #17112; CHECK-NEXT: ushr v0.16b, v0.16b, #3113; CHECK-NEXT: movi v2.16b, #15114; CHECK-NEXT: and v0.16b, v0.16b, v1.16b115; CHECK-NEXT: mul v0.16b, v0.16b, v2.16b116; CHECK-NEXT: ret117 %b = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>118 %c = and <16 x i8> %b, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17>119 %d = mul nuw <16 x i8> %c, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15>120 ret <16 x i8> %d121}122 123