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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6;7; VECTOR_SPLICE (index)8;9 10define <vscale x 16 x i8> @splice_nxv16i8_zero_idx(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {11; CHECK-LABEL: splice_nxv16i8_zero_idx:12; CHECK: // %bb.0:13; CHECK-NEXT: ret14 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 0)15 ret <vscale x 16 x i8> %res16}17 18define <vscale x 16 x i8> @splice_nxv16i8_first_idx(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {19; CHECK-LABEL: splice_nxv16i8_first_idx:20; CHECK: // %bb.0:21; CHECK-NEXT: ext z0.b, z0.b, z1.b, #122; CHECK-NEXT: ret23 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 1)24 ret <vscale x 16 x i8> %res25}26 27define <vscale x 16 x i8> @splice_nxv16i8_last_idx(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) vscale_range(16,16) #0 {28; CHECK-LABEL: splice_nxv16i8_last_idx:29; CHECK: // %bb.0:30; CHECK-NEXT: ext z0.b, z0.b, z1.b, #25531; CHECK-NEXT: ret32 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 255)33 ret <vscale x 16 x i8> %res34}35 36define <vscale x 16 x i8> @splice_nxv16i8_first_idx_unary(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {37; CHECK-LABEL: splice_nxv16i8_first_idx_unary:38; CHECK: // %bb.0:39; CHECK-NEXT: movprfx z0, z140; CHECK-NEXT: ext z0.b, z0.b, z1.b, #141; CHECK-NEXT: ret42 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %b, <vscale x 16 x i8> %b, i32 1)43 ret <vscale x 16 x i8> %res44}45 46define <vscale x 8 x i16> @splice_nxv8i16_first_idx(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {47; CHECK-LABEL: splice_nxv8i16_first_idx:48; CHECK: // %bb.0:49; CHECK-NEXT: ext z0.b, z0.b, z1.b, #250; CHECK-NEXT: ret51 %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 1)52 ret <vscale x 8 x i16> %res53}54 55define <vscale x 8 x i16> @splice_nxv8i16_first_idx_unary(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {56; CHECK-LABEL: splice_nxv8i16_first_idx_unary:57; CHECK: // %bb.0:58; CHECK-NEXT: movprfx z0, z159; CHECK-NEXT: ext z0.b, z0.b, z1.b, #260; CHECK-NEXT: ret61 %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %b, <vscale x 8 x i16> %b, i32 1)62 ret <vscale x 8 x i16> %res63}64 65define <vscale x 4 x i32> @splice_nxv4i32_first_idx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {66; CHECK-LABEL: splice_nxv4i32_first_idx:67; CHECK: // %bb.0:68; CHECK-NEXT: ext z0.b, z0.b, z1.b, #469; CHECK-NEXT: ret70 %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 1)71 ret <vscale x 4 x i32> %res72}73 74define <vscale x 4 x i32> @splice_nxv4i32_last_idx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) vscale_range(16,16) #0 {75; CHECK-LABEL: splice_nxv4i32_last_idx:76; CHECK: // %bb.0:77; CHECK-NEXT: ext z0.b, z0.b, z1.b, #25278; CHECK-NEXT: ret79 %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 63)80 ret <vscale x 4 x i32> %res81}82 83define <vscale x 4 x i32> @splice_nxv4i32_first_idx_unary(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {84; CHECK-LABEL: splice_nxv4i32_first_idx_unary:85; CHECK: // %bb.0:86; CHECK-NEXT: movprfx z0, z187; CHECK-NEXT: ext z0.b, z0.b, z1.b, #488; CHECK-NEXT: ret89 %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %b, <vscale x 4 x i32> %b, i32 1)90 ret <vscale x 4 x i32> %res91}92 93define <vscale x 2 x i64> @splice_nxv2i64_first_idx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {94; CHECK-LABEL: splice_nxv2i64_first_idx:95; CHECK: // %bb.0:96; CHECK-NEXT: ext z0.b, z0.b, z1.b, #897; CHECK-NEXT: ret98 %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 1)99 ret <vscale x 2 x i64> %res100}101 102define <vscale x 2 x i64> @splice_nxv2i64_last_idx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) vscale_range(16,16) #0 {103; CHECK-LABEL: splice_nxv2i64_last_idx:104; CHECK: // %bb.0:105; CHECK-NEXT: ext z0.b, z0.b, z1.b, #248106; CHECK-NEXT: ret107 %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 31)108 ret <vscale x 2 x i64> %res109}110 111define <vscale x 2 x i64> @splice_nxv2i64_first_idx_unary(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {112; CHECK-LABEL: splice_nxv2i64_first_idx_unary:113; CHECK: // %bb.0:114; CHECK-NEXT: movprfx z0, z1115; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8116; CHECK-NEXT: ret117 %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %b, <vscale x 2 x i64> %b, i32 1)118 ret <vscale x 2 x i64> %res119}120 121define <vscale x 2 x half> @splice_nxv2f16_neg_idx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {122; CHECK-LABEL: splice_nxv2f16_neg_idx:123; CHECK: // %bb.0:124; CHECK-NEXT: ptrue p0.d, vl1125; CHECK-NEXT: rev p0.d, p0.d126; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d127; CHECK-NEXT: ret128 %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -1)129 ret <vscale x 2 x half> %res130}131 132define <vscale x 2 x half> @splice_nxv2f16_neg2_idx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {133; CHECK-LABEL: splice_nxv2f16_neg2_idx:134; CHECK: // %bb.0:135; CHECK-NEXT: ptrue p0.d, vl2136; CHECK-NEXT: rev p0.d, p0.d137; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d138; CHECK-NEXT: ret139 %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -2)140 ret <vscale x 2 x half> %res141}142 143define <vscale x 2 x half> @splice_nxv2f16_neg_idx_unary(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {144; CHECK-LABEL: splice_nxv2f16_neg_idx_unary:145; CHECK: // %bb.0:146; CHECK-NEXT: ptrue p0.d, vl1147; CHECK-NEXT: mov z0.d, z1.d148; CHECK-NEXT: rev p0.d, p0.d149; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d150; CHECK-NEXT: ret151 %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %b, <vscale x 2 x half> %b, i32 -1)152 ret <vscale x 2 x half> %res153}154 155define <vscale x 2 x half> @splice_nxv2f16_first_idx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {156; CHECK-LABEL: splice_nxv2f16_first_idx:157; CHECK: // %bb.0:158; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8159; CHECK-NEXT: ret160 %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 1)161 ret <vscale x 2 x half> %res162}163 164define <vscale x 2 x half> @splice_nxv2f16_last_idx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) vscale_range(16,16) #0 {165; CHECK-LABEL: splice_nxv2f16_last_idx:166; CHECK: // %bb.0:167; CHECK-NEXT: ext z0.b, z0.b, z1.b, #248168; CHECK-NEXT: ret169 %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 31)170 ret <vscale x 2 x half> %res171}172 173define <vscale x 2 x half> @splice_nxv2f16_first_idx_unary(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {174; CHECK-LABEL: splice_nxv2f16_first_idx_unary:175; CHECK: // %bb.0:176; CHECK-NEXT: movprfx z0, z1177; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8178; CHECK-NEXT: ret179 %res = call <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half> %b, <vscale x 2 x half> %b, i32 1)180 ret <vscale x 2 x half> %res181}182 183define <vscale x 4 x half> @splice_nxv4f16_neg_idx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {184; CHECK-LABEL: splice_nxv4f16_neg_idx:185; CHECK: // %bb.0:186; CHECK-NEXT: ptrue p0.s, vl1187; CHECK-NEXT: rev p0.s, p0.s188; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s189; CHECK-NEXT: ret190 %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -1)191 ret <vscale x 4 x half> %res192}193 194define <vscale x 4 x half> @splice_nxv4f16_neg3_idx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {195; CHECK-LABEL: splice_nxv4f16_neg3_idx:196; CHECK: // %bb.0:197; CHECK-NEXT: ptrue p0.s, vl3198; CHECK-NEXT: rev p0.s, p0.s199; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s200; CHECK-NEXT: ret201 %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -3)202 ret <vscale x 4 x half> %res203}204 205define <vscale x 4 x half> @splice_nxv4f16_neg_idx_unary(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {206; CHECK-LABEL: splice_nxv4f16_neg_idx_unary:207; CHECK: // %bb.0:208; CHECK-NEXT: ptrue p0.s, vl1209; CHECK-NEXT: mov z0.d, z1.d210; CHECK-NEXT: rev p0.s, p0.s211; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s212; CHECK-NEXT: ret213 %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %b, <vscale x 4 x half> %b, i32 -1)214 ret <vscale x 4 x half> %res215}216 217define <vscale x 4 x half> @splice_nxv4f16_first_idx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {218; CHECK-LABEL: splice_nxv4f16_first_idx:219; CHECK: // %bb.0:220; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4221; CHECK-NEXT: ret222 %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 1)223 ret <vscale x 4 x half> %res224}225 226define <vscale x 4 x half> @splice_nxv4f16_last_idx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) vscale_range(16,16) #0 {227; CHECK-LABEL: splice_nxv4f16_last_idx:228; CHECK: // %bb.0:229; CHECK-NEXT: ext z0.b, z0.b, z1.b, #252230; CHECK-NEXT: ret231 %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 63)232 ret <vscale x 4 x half> %res233}234 235define <vscale x 4 x half> @splice_nxv4f16_first_idx_unary(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {236; CHECK-LABEL: splice_nxv4f16_first_idx_unary:237; CHECK: // %bb.0:238; CHECK-NEXT: movprfx z0, z1239; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4240; CHECK-NEXT: ret241 %res = call <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half> %b, <vscale x 4 x half> %b, i32 1)242 ret <vscale x 4 x half> %res243}244 245define <vscale x 8 x half> @splice_nxv8f16_first_idx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {246; CHECK-LABEL: splice_nxv8f16_first_idx:247; CHECK: // %bb.0:248; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2249; CHECK-NEXT: ret250 %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 1)251 ret <vscale x 8 x half> %res252}253 254define <vscale x 8 x half> @splice_nxv8f16_last_idx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) vscale_range(16,16) #0 {255; CHECK-LABEL: splice_nxv8f16_last_idx:256; CHECK: // %bb.0:257; CHECK-NEXT: ext z0.b, z0.b, z1.b, #254258; CHECK-NEXT: ret259 %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 127)260 ret <vscale x 8 x half> %res261}262 263define <vscale x 8 x half> @splice_nxv8f16_first_idx_unary(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {264; CHECK-LABEL: splice_nxv8f16_first_idx_unary:265; CHECK: // %bb.0:266; CHECK-NEXT: movprfx z0, z1267; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2268; CHECK-NEXT: ret269 %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %b, <vscale x 8 x half> %b, i32 1)270 ret <vscale x 8 x half> %res271}272 273define <vscale x 2 x float> @splice_nxv2f32_neg_idx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {274; CHECK-LABEL: splice_nxv2f32_neg_idx:275; CHECK: // %bb.0:276; CHECK-NEXT: ptrue p0.d, vl1277; CHECK-NEXT: rev p0.d, p0.d278; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d279; CHECK-NEXT: ret280 %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -1)281 ret <vscale x 2 x float> %res282}283 284define <vscale x 2 x float> @splice_nxv2f32_neg2_idx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {285; CHECK-LABEL: splice_nxv2f32_neg2_idx:286; CHECK: // %bb.0:287; CHECK-NEXT: ptrue p0.d, vl2288; CHECK-NEXT: rev p0.d, p0.d289; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d290; CHECK-NEXT: ret291 %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -2)292 ret <vscale x 2 x float> %res293}294 295define <vscale x 2 x float> @splice_nxv2f32_neg_idx_unary(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {296; CHECK-LABEL: splice_nxv2f32_neg_idx_unary:297; CHECK: // %bb.0:298; CHECK-NEXT: ptrue p0.d, vl1299; CHECK-NEXT: mov z0.d, z1.d300; CHECK-NEXT: rev p0.d, p0.d301; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d302; CHECK-NEXT: ret303 %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %b, <vscale x 2 x float> %b, i32 -1)304 ret <vscale x 2 x float> %res305}306 307define <vscale x 2 x float> @splice_nxv2f32_first_idx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {308; CHECK-LABEL: splice_nxv2f32_first_idx:309; CHECK: // %bb.0:310; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8311; CHECK-NEXT: ret312 %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 1)313 ret <vscale x 2 x float> %res314}315 316define <vscale x 2 x float> @splice_nxv2f32_last_idx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) vscale_range(16,16) #0 {317; CHECK-LABEL: splice_nxv2f32_last_idx:318; CHECK: // %bb.0:319; CHECK-NEXT: ext z0.b, z0.b, z1.b, #248320; CHECK-NEXT: ret321 %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 31)322 ret <vscale x 2 x float> %res323}324 325define <vscale x 2 x float> @splice_nxv2f32_first_idx_unary(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {326; CHECK-LABEL: splice_nxv2f32_first_idx_unary:327; CHECK: // %bb.0:328; CHECK-NEXT: movprfx z0, z1329; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8330; CHECK-NEXT: ret331 %res = call <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float> %b, <vscale x 2 x float> %b, i32 1)332 ret <vscale x 2 x float> %res333}334 335define <vscale x 4 x float> @splice_nxv4f32_first_idx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {336; CHECK-LABEL: splice_nxv4f32_first_idx:337; CHECK: // %bb.0:338; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4339; CHECK-NEXT: ret340 %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 1)341 ret <vscale x 4 x float> %res342}343 344define <vscale x 4 x float> @splice_nxv4f32_last_idx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) vscale_range(16,16) #0 {345; CHECK-LABEL: splice_nxv4f32_last_idx:346; CHECK: // %bb.0:347; CHECK-NEXT: ext z0.b, z0.b, z1.b, #252348; CHECK-NEXT: ret349 %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 63)350 ret <vscale x 4 x float> %res351}352 353define <vscale x 4 x float> @splice_nxv4f32_first_idx_unary(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {354; CHECK-LABEL: splice_nxv4f32_first_idx_unary:355; CHECK: // %bb.0:356; CHECK-NEXT: movprfx z0, z1357; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4358; CHECK-NEXT: ret359 %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %b, <vscale x 4 x float> %b, i32 1)360 ret <vscale x 4 x float> %res361}362 363define <vscale x 2 x double> @splice_nxv2f64_first_idx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {364; CHECK-LABEL: splice_nxv2f64_first_idx:365; CHECK: // %bb.0:366; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8367; CHECK-NEXT: ret368 %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 1)369 ret <vscale x 2 x double> %res370}371 372define <vscale x 2 x double> @splice_nxv2f64_last_idx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) vscale_range(16,16) #0 {373; CHECK-LABEL: splice_nxv2f64_last_idx:374; CHECK: // %bb.0:375; CHECK-NEXT: ext z0.b, z0.b, z1.b, #248376; CHECK-NEXT: ret377 %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 31)378 ret <vscale x 2 x double> %res379}380 381define <vscale x 2 x double> @splice_nxv2f64_first_idx_unary(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {382; CHECK-LABEL: splice_nxv2f64_first_idx_unary:383; CHECK: // %bb.0:384; CHECK-NEXT: movprfx z0, z1385; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8386; CHECK-NEXT: ret387 %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %b, <vscale x 2 x double> %b, i32 1)388 ret <vscale x 2 x double> %res389}390 391; Ensure predicate based splice is promoted to use ZPRs.392define <vscale x 2 x i1> @splice_nxv2i1_idx(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) #0 {393; CHECK-LABEL: splice_nxv2i1_idx:394; CHECK: // %bb.0:395; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1396; CHECK-NEXT: mov z1.d, p0/z, #1 // =0x1397; CHECK-NEXT: ptrue p0.d398; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8399; CHECK-NEXT: and z1.d, z1.d, #0x1400; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0401; CHECK-NEXT: ret402 %res = call <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i32 1)403 ret <vscale x 2 x i1> %res404}405 406; Ensure predicate based splice is promoted to use ZPRs.407define <vscale x 4 x i1> @splice_nxv4i1_idx(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) #0 {408; CHECK-LABEL: splice_nxv4i1_idx:409; CHECK: // %bb.0:410; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1411; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x1412; CHECK-NEXT: ptrue p0.s413; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8414; CHECK-NEXT: and z1.s, z1.s, #0x1415; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #0416; CHECK-NEXT: ret417 %res = call <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i32 2)418 ret <vscale x 4 x i1> %res419}420 421; Ensure predicate based splice is promoted to use ZPRs.422define <vscale x 8 x i1> @splice_nxv8i1_idx(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) #0 {423; CHECK-LABEL: splice_nxv8i1_idx:424; CHECK: // %bb.0:425; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x1426; CHECK-NEXT: mov z1.h, p0/z, #1 // =0x1427; CHECK-NEXT: ptrue p0.h428; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8429; CHECK-NEXT: and z1.h, z1.h, #0x1430; CHECK-NEXT: cmpne p0.h, p0/z, z1.h, #0431; CHECK-NEXT: ret432 %res = call <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i32 4)433 ret <vscale x 8 x i1> %res434}435 436; Ensure predicate based splice is promoted to use ZPRs.437define <vscale x 16 x i1> @splice_nxv16i1_idx(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {438; CHECK-LABEL: splice_nxv16i1_idx:439; CHECK: // %bb.0:440; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x1441; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x1442; CHECK-NEXT: ptrue p0.b443; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8444; CHECK-NEXT: and z1.b, z1.b, #0x1445; CHECK-NEXT: cmpne p0.b, p0/z, z1.b, #0446; CHECK-NEXT: ret447 %res = call <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i32 8)448 ret <vscale x 16 x i1> %res449}450 451; Verify promote type legalisation works as expected.452define <vscale x 2 x i8> @splice_nxv2i8_idx(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {453; CHECK-LABEL: splice_nxv2i8_idx:454; CHECK: // %bb.0:455; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8456; CHECK-NEXT: ret457 %res = call <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 1)458 ret <vscale x 2 x i8> %res459}460 461; Verify splitvec type legalisation works as expected.462define <vscale x 8 x i32> @splice_nxv8i32_idx(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {463; CHECK-LABEL: splice_nxv8i32_idx:464; CHECK: // %bb.0:465; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill466; CHECK-NEXT: addvl sp, sp, #-4467; CHECK-NEXT: mov x8, sp468; CHECK-NEXT: str z1, [sp, #1, mul vl]469; CHECK-NEXT: str z0, [sp]470; CHECK-NEXT: orr x8, x8, #0x8471; CHECK-NEXT: str z3, [sp, #3, mul vl]472; CHECK-NEXT: str z2, [sp, #2, mul vl]473; CHECK-NEXT: ldr z0, [x8]474; CHECK-NEXT: ldr z1, [x8, #1, mul vl]475; CHECK-NEXT: addvl sp, sp, #4476; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload477; CHECK-NEXT: ret478 %res = call <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 2)479 ret <vscale x 8 x i32> %res480}481 482; Verify splitvec type legalisation works as expected.483define <vscale x 16 x float> @splice_nxv16f32_16(<vscale x 16 x float> %a, <vscale x 16 x float> %b) vscale_range(2,16) #0 {484; CHECK-LABEL: splice_nxv16f32_16:485; CHECK: // %bb.0:486; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill487; CHECK-NEXT: addvl sp, sp, #-8488; CHECK-NEXT: rdvl x8, #1489; CHECK-NEXT: mov w9, #16 // =0x10490; CHECK-NEXT: ptrue p0.s491; CHECK-NEXT: sub x8, x8, #1492; CHECK-NEXT: str z3, [sp, #3, mul vl]493; CHECK-NEXT: cmp x8, #16494; CHECK-NEXT: str z2, [sp, #2, mul vl]495; CHECK-NEXT: csel x8, x8, x9, lo496; CHECK-NEXT: mov x9, sp497; CHECK-NEXT: str z1, [sp, #1, mul vl]498; CHECK-NEXT: add x10, x9, x8, lsl #2499; CHECK-NEXT: str z0, [sp]500; CHECK-NEXT: str z7, [sp, #7, mul vl]501; CHECK-NEXT: str z4, [sp, #4, mul vl]502; CHECK-NEXT: str z5, [sp, #5, mul vl]503; CHECK-NEXT: str z6, [sp, #6, mul vl]504; CHECK-NEXT: ld1w { z0.s }, p0/z, [x9, x8, lsl #2]505; CHECK-NEXT: ldr z1, [x10, #1, mul vl]506; CHECK-NEXT: ldr z2, [x10, #2, mul vl]507; CHECK-NEXT: ldr z3, [x10, #3, mul vl]508; CHECK-NEXT: addvl sp, sp, #8509; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload510; CHECK-NEXT: ret511 %res = call <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 16)512 ret <vscale x 16 x float> %res513}514 515;516; VECTOR_SPLICE (trailing elements)517;518 519define <vscale x 16 x i8> @splice_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {520; CHECK-LABEL: splice_nxv16i8:521; CHECK: // %bb.0:522; CHECK-NEXT: ptrue p0.b, vl16523; CHECK-NEXT: rev p0.b, p0.b524; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b525; CHECK-NEXT: ret526 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -16)527 ret <vscale x 16 x i8> %res528}529 530define <vscale x 16 x i8> @splice_nxv16i8_neg32(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) vscale_range(2,16) #0 {531; CHECK-LABEL: splice_nxv16i8_neg32:532; CHECK: // %bb.0:533; CHECK-NEXT: ptrue p0.b, vl32534; CHECK-NEXT: rev p0.b, p0.b535; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b536; CHECK-NEXT: ret537 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -32)538 ret <vscale x 16 x i8> %res539}540 541define <vscale x 16 x i8> @splice_nxv16i8_neg64(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) vscale_range(4,16) #0 {542; CHECK-LABEL: splice_nxv16i8_neg64:543; CHECK: // %bb.0:544; CHECK-NEXT: ptrue p0.b, vl64545; CHECK-NEXT: rev p0.b, p0.b546; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b547; CHECK-NEXT: ret548 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -64)549 ret <vscale x 16 x i8> %res550}551 552define <vscale x 16 x i8> @splice_nxv16i8_neg128(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) vscale_range(8,16) #0 {553; CHECK-LABEL: splice_nxv16i8_neg128:554; CHECK: // %bb.0:555; CHECK-NEXT: ptrue p0.b, vl128556; CHECK-NEXT: rev p0.b, p0.b557; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b558; CHECK-NEXT: ret559 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -128)560 ret <vscale x 16 x i8> %res561}562 563define <vscale x 16 x i8> @splice_nxv16i8_neg256(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) vscale_range(16,16) #0 {564; CHECK-LABEL: splice_nxv16i8_neg256:565; CHECK: // %bb.0:566; CHECK-NEXT: ptrue p0.b, vl256567; CHECK-NEXT: rev p0.b, p0.b568; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b569; CHECK-NEXT: ret570 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -256)571 ret <vscale x 16 x i8> %res572}573 574define <vscale x 16 x i8> @splice_nxv16i8_1(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {575; CHECK-LABEL: splice_nxv16i8_1:576; CHECK: // %bb.0:577; CHECK-NEXT: ptrue p0.b, vl1578; CHECK-NEXT: rev p0.b, p0.b579; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b580; CHECK-NEXT: ret581 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -1)582 ret <vscale x 16 x i8> %res583}584 585define <vscale x 16 x i8> @splice_nxv16i8_neg17(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) vscale_range(2,16) #0 {586; CHECK-LABEL: splice_nxv16i8_neg17:587; CHECK: // %bb.0:588; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill589; CHECK-NEXT: addvl sp, sp, #-2590; CHECK-NEXT: rdvl x8, #1591; CHECK-NEXT: mov w9, #17 // =0x11592; CHECK-NEXT: mov x10, sp593; CHECK-NEXT: cmp x8, #17594; CHECK-NEXT: str z0, [sp]595; CHECK-NEXT: csel x9, x8, x9, lo596; CHECK-NEXT: add x8, x10, x8597; CHECK-NEXT: str z1, [sp, #1, mul vl]598; CHECK-NEXT: sub x8, x8, x9599; CHECK-NEXT: ldr z0, [x8]600; CHECK-NEXT: addvl sp, sp, #2601; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload602; CHECK-NEXT: ret603 %res = call <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -17)604 ret <vscale x 16 x i8> %res605}606 607define <vscale x 8 x i16> @splice_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {608; CHECK-LABEL: splice_nxv8i16:609; CHECK: // %bb.0:610; CHECK-NEXT: ptrue p0.h, vl8611; CHECK-NEXT: rev p0.h, p0.h612; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h613; CHECK-NEXT: ret614 %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -8)615 ret <vscale x 8 x i16> %res616}617 618define <vscale x 8 x i16> @splice_nxv8i16_1(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {619; CHECK-LABEL: splice_nxv8i16_1:620; CHECK: // %bb.0:621; CHECK-NEXT: ptrue p0.h, vl1622; CHECK-NEXT: rev p0.h, p0.h623; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h624; CHECK-NEXT: ret625 %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -1)626 ret <vscale x 8 x i16> %res627}628 629define <vscale x 8 x i16> @splice_nxv8i16_neg9(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) vscale_range(2,16) #0 {630; CHECK-LABEL: splice_nxv8i16_neg9:631; CHECK: // %bb.0:632; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill633; CHECK-NEXT: addvl sp, sp, #-2634; CHECK-NEXT: rdvl x8, #1635; CHECK-NEXT: mov w9, #18 // =0x12636; CHECK-NEXT: mov x10, sp637; CHECK-NEXT: cmp x8, #18638; CHECK-NEXT: str z0, [sp]639; CHECK-NEXT: csel x9, x8, x9, lo640; CHECK-NEXT: add x8, x10, x8641; CHECK-NEXT: str z1, [sp, #1, mul vl]642; CHECK-NEXT: sub x8, x8, x9643; CHECK-NEXT: ldr z0, [x8]644; CHECK-NEXT: addvl sp, sp, #2645; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload646; CHECK-NEXT: ret647 %res = call <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -9)648 ret <vscale x 8 x i16> %res649}650 651define <vscale x 4 x i32> @splice_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {652; CHECK-LABEL: splice_nxv4i32:653; CHECK: // %bb.0:654; CHECK-NEXT: ptrue p0.s, vl4655; CHECK-NEXT: rev p0.s, p0.s656; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s657; CHECK-NEXT: ret658 %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -4)659 ret <vscale x 4 x i32> %res660}661 662define <vscale x 4 x i32> @splice_nxv4i32_1(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {663; CHECK-LABEL: splice_nxv4i32_1:664; CHECK: // %bb.0:665; CHECK-NEXT: ptrue p0.s, vl1666; CHECK-NEXT: rev p0.s, p0.s667; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s668; CHECK-NEXT: ret669 %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -1)670 ret <vscale x 4 x i32> %res671}672 673define <vscale x 4 x i32> @splice_nxv4i32_neg5(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) vscale_range(2,16) #0 {674; CHECK-LABEL: splice_nxv4i32_neg5:675; CHECK: // %bb.0:676; CHECK-NEXT: ptrue p0.s, vl5677; CHECK-NEXT: rev p0.s, p0.s678; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s679; CHECK-NEXT: ret680 %res = call <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -5)681 ret <vscale x 4 x i32> %res682}683 684define <vscale x 2 x i64> @splice_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {685; CHECK-LABEL: splice_nxv2i64:686; CHECK: // %bb.0:687; CHECK-NEXT: ptrue p0.d, vl2688; CHECK-NEXT: rev p0.d, p0.d689; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d690; CHECK-NEXT: ret691 %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -2)692 ret <vscale x 2 x i64> %res693}694 695define <vscale x 2 x i64> @splice_nxv2i64_1(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {696; CHECK-LABEL: splice_nxv2i64_1:697; CHECK: // %bb.0:698; CHECK-NEXT: ptrue p0.d, vl1699; CHECK-NEXT: rev p0.d, p0.d700; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d701; CHECK-NEXT: ret702 %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -1)703 ret <vscale x 2 x i64> %res704}705 706define <vscale x 2 x i64> @splice_nxv2i64_neg3(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) vscale_range(2,16) #0 {707; CHECK-LABEL: splice_nxv2i64_neg3:708; CHECK: // %bb.0:709; CHECK-NEXT: ptrue p0.d, vl3710; CHECK-NEXT: rev p0.d, p0.d711; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d712; CHECK-NEXT: ret713 %res = call <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -3)714 ret <vscale x 2 x i64> %res715}716 717define <vscale x 8 x half> @splice_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {718; CHECK-LABEL: splice_nxv8f16:719; CHECK: // %bb.0:720; CHECK-NEXT: ptrue p0.h, vl8721; CHECK-NEXT: rev p0.h, p0.h722; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h723; CHECK-NEXT: ret724 %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -8)725 ret <vscale x 8 x half> %res726}727 728define <vscale x 8 x half> @splice_nxv8f16_1(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {729; CHECK-LABEL: splice_nxv8f16_1:730; CHECK: // %bb.0:731; CHECK-NEXT: ptrue p0.h, vl1732; CHECK-NEXT: rev p0.h, p0.h733; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h734; CHECK-NEXT: ret735 %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -1)736 ret <vscale x 8 x half> %res737}738 739define <vscale x 8 x half> @splice_nxv8f16_neg9(<vscale x 8 x half> %a, <vscale x 8 x half> %b) vscale_range(2,16) #0 {740; CHECK-LABEL: splice_nxv8f16_neg9:741; CHECK: // %bb.0:742; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill743; CHECK-NEXT: addvl sp, sp, #-2744; CHECK-NEXT: rdvl x8, #1745; CHECK-NEXT: mov w9, #18 // =0x12746; CHECK-NEXT: mov x10, sp747; CHECK-NEXT: cmp x8, #18748; CHECK-NEXT: str z0, [sp]749; CHECK-NEXT: csel x9, x8, x9, lo750; CHECK-NEXT: add x8, x10, x8751; CHECK-NEXT: str z1, [sp, #1, mul vl]752; CHECK-NEXT: sub x8, x8, x9753; CHECK-NEXT: ldr z0, [x8]754; CHECK-NEXT: addvl sp, sp, #2755; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload756; CHECK-NEXT: ret757 %res = call <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -9)758 ret <vscale x 8 x half> %res759}760 761define <vscale x 4 x float> @splice_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {762; CHECK-LABEL: splice_nxv4f32:763; CHECK: // %bb.0:764; CHECK-NEXT: ptrue p0.s, vl4765; CHECK-NEXT: rev p0.s, p0.s766; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s767; CHECK-NEXT: ret768 %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -4)769 ret <vscale x 4 x float> %res770}771 772define <vscale x 4 x float> @splice_nxv4f32_1(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {773; CHECK-LABEL: splice_nxv4f32_1:774; CHECK: // %bb.0:775; CHECK-NEXT: ptrue p0.s, vl1776; CHECK-NEXT: rev p0.s, p0.s777; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s778; CHECK-NEXT: ret779 %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -1)780 ret <vscale x 4 x float> %res781}782 783define <vscale x 4 x float> @splice_nxv4f32_neg5(<vscale x 4 x float> %a, <vscale x 4 x float> %b) vscale_range(2,16) #0 {784; CHECK-LABEL: splice_nxv4f32_neg5:785; CHECK: // %bb.0:786; CHECK-NEXT: ptrue p0.s, vl5787; CHECK-NEXT: rev p0.s, p0.s788; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s789; CHECK-NEXT: ret790 %res = call <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -5)791 ret <vscale x 4 x float> %res792}793 794define <vscale x 2 x double> @splice_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {795; CHECK-LABEL: splice_nxv2f64:796; CHECK: // %bb.0:797; CHECK-NEXT: ptrue p0.d, vl2798; CHECK-NEXT: rev p0.d, p0.d799; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d800; CHECK-NEXT: ret801 %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -2)802 ret <vscale x 2 x double> %res803}804 805define <vscale x 2 x double> @splice_nxv2f64_1(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {806; CHECK-LABEL: splice_nxv2f64_1:807; CHECK: // %bb.0:808; CHECK-NEXT: ptrue p0.d, vl1809; CHECK-NEXT: rev p0.d, p0.d810; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d811; CHECK-NEXT: ret812 %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -1)813 ret <vscale x 2 x double> %res814}815 816define <vscale x 2 x double> @splice_nxv2f64_neg3(<vscale x 2 x double> %a, <vscale x 2 x double> %b) vscale_range(2,16) #0 {817; CHECK-LABEL: splice_nxv2f64_neg3:818; CHECK: // %bb.0:819; CHECK-NEXT: ptrue p0.d, vl3820; CHECK-NEXT: rev p0.d, p0.d821; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d822; CHECK-NEXT: ret823 %res = call <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -3)824 ret <vscale x 2 x double> %res825}826 827define <vscale x 2 x bfloat> @splice_nxv2bf16_neg_idx(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {828; CHECK-LABEL: splice_nxv2bf16_neg_idx:829; CHECK: // %bb.0:830; CHECK-NEXT: ptrue p0.d, vl1831; CHECK-NEXT: rev p0.d, p0.d832; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d833; CHECK-NEXT: ret834 %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 -1)835 ret <vscale x 2 x bfloat> %res836}837 838define <vscale x 2 x bfloat> @splice_nxv2bf16_neg2_idx(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {839; CHECK-LABEL: splice_nxv2bf16_neg2_idx:840; CHECK: // %bb.0:841; CHECK-NEXT: ptrue p0.d, vl2842; CHECK-NEXT: rev p0.d, p0.d843; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d844; CHECK-NEXT: ret845 %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 -2)846 ret <vscale x 2 x bfloat> %res847}848 849define <vscale x 2 x bfloat> @splice_nxv2bf16_neg_idx_unary(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {850; CHECK-LABEL: splice_nxv2bf16_neg_idx_unary:851; CHECK: // %bb.0:852; CHECK-NEXT: ptrue p0.d, vl1853; CHECK-NEXT: mov z0.d, z1.d854; CHECK-NEXT: rev p0.d, p0.d855; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d856; CHECK-NEXT: ret857 %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %b, <vscale x 2 x bfloat> %b, i32 -1)858 ret <vscale x 2 x bfloat> %res859}860 861define <vscale x 2 x bfloat> @splice_nxv2bf16_first_idx(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {862; CHECK-LABEL: splice_nxv2bf16_first_idx:863; CHECK: // %bb.0:864; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8865; CHECK-NEXT: ret866 %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 1)867 ret <vscale x 2 x bfloat> %res868}869 870define <vscale x 2 x bfloat> @splice_nxv2bf16_last_idx(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) vscale_range(16,16) #0 {871; CHECK-LABEL: splice_nxv2bf16_last_idx:872; CHECK: // %bb.0:873; CHECK-NEXT: ext z0.b, z0.b, z1.b, #248874; CHECK-NEXT: ret875 %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b, i32 31)876 ret <vscale x 2 x bfloat> %res877}878 879define <vscale x 2 x bfloat> @splice_nxv2bf16_first_idx_unary(<vscale x 2 x bfloat> %a, <vscale x 2 x bfloat> %b) #0 {880; CHECK-LABEL: splice_nxv2bf16_first_idx_unary:881; CHECK: // %bb.0:882; CHECK-NEXT: movprfx z0, z1883; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8884; CHECK-NEXT: ret885 %res = call <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat> %b, <vscale x 2 x bfloat> %b, i32 1)886 ret <vscale x 2 x bfloat> %res887}888 889define <vscale x 4 x bfloat> @splice_nxv4bf16_neg_idx(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {890; CHECK-LABEL: splice_nxv4bf16_neg_idx:891; CHECK: // %bb.0:892; CHECK-NEXT: ptrue p0.s, vl1893; CHECK-NEXT: rev p0.s, p0.s894; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s895; CHECK-NEXT: ret896 %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 -1)897 ret <vscale x 4 x bfloat> %res898}899 900define <vscale x 4 x bfloat> @splice_nxv4bf16_neg3_idx(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {901; CHECK-LABEL: splice_nxv4bf16_neg3_idx:902; CHECK: // %bb.0:903; CHECK-NEXT: ptrue p0.s, vl3904; CHECK-NEXT: rev p0.s, p0.s905; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s906; CHECK-NEXT: ret907 %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 -3)908 ret <vscale x 4 x bfloat> %res909}910 911define <vscale x 4 x bfloat> @splice_nxv4bf16_neg_idx_unary(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {912; CHECK-LABEL: splice_nxv4bf16_neg_idx_unary:913; CHECK: // %bb.0:914; CHECK-NEXT: ptrue p0.s, vl1915; CHECK-NEXT: mov z0.d, z1.d916; CHECK-NEXT: rev p0.s, p0.s917; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s918; CHECK-NEXT: ret919 %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %b, i32 -1)920 ret <vscale x 4 x bfloat> %res921}922 923define <vscale x 4 x bfloat> @splice_nxv4bf16_first_idx(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {924; CHECK-LABEL: splice_nxv4bf16_first_idx:925; CHECK: // %bb.0:926; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4927; CHECK-NEXT: ret928 %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 1)929 ret <vscale x 4 x bfloat> %res930}931 932define <vscale x 4 x bfloat> @splice_nxv4bf16_last_idx(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) vscale_range(16,16) #0 {933; CHECK-LABEL: splice_nxv4bf16_last_idx:934; CHECK: // %bb.0:935; CHECK-NEXT: ext z0.b, z0.b, z1.b, #252936; CHECK-NEXT: ret937 %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b, i32 63)938 ret <vscale x 4 x bfloat> %res939}940 941define <vscale x 4 x bfloat> @splice_nxv4bf16_first_idx_unary(<vscale x 4 x bfloat> %a, <vscale x 4 x bfloat> %b) #0 {942; CHECK-LABEL: splice_nxv4bf16_first_idx_unary:943; CHECK: // %bb.0:944; CHECK-NEXT: movprfx z0, z1945; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4946; CHECK-NEXT: ret947 %res = call <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %b, i32 1)948 ret <vscale x 4 x bfloat> %res949}950 951define <vscale x 8 x bfloat> @splice_nxv8bf16_first_idx(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {952; CHECK-LABEL: splice_nxv8bf16_first_idx:953; CHECK: // %bb.0:954; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2955; CHECK-NEXT: ret956 %res = call <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i32 1)957 ret <vscale x 8 x bfloat> %res958}959 960define <vscale x 8 x bfloat> @splice_nxv8bf16_last_idx(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) vscale_range(16,16) #0 {961; CHECK-LABEL: splice_nxv8bf16_last_idx:962; CHECK: // %bb.0:963; CHECK-NEXT: ext z0.b, z0.b, z1.b, #254964; CHECK-NEXT: ret965 %res = call <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b, i32 127)966 ret <vscale x 8 x bfloat> %res967}968 969define <vscale x 8 x bfloat> @splice_nxv8bf16_first_idx_unary(<vscale x 8 x bfloat> %a, <vscale x 8 x bfloat> %b) #0 {970; CHECK-LABEL: splice_nxv8bf16_first_idx_unary:971; CHECK: // %bb.0:972; CHECK-NEXT: movprfx z0, z1973; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2974; CHECK-NEXT: ret975 %res = call <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %b, i32 1)976 ret <vscale x 8 x bfloat> %res977}978 979; Ensure predicate based splice is promoted to use ZPRs.980define <vscale x 2 x i1> @splice_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b) #0 {981; CHECK-LABEL: splice_nxv2i1:982; CHECK: // %bb.0:983; CHECK-NEXT: ptrue p2.d, vl1984; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1985; CHECK-NEXT: mov z1.d, p0/z, #1 // =0x1986; CHECK-NEXT: rev p0.d, p2.d987; CHECK-NEXT: splice z1.d, p0, z1.d, z0.d988; CHECK-NEXT: ptrue p0.d989; CHECK-NEXT: and z1.d, z1.d, #0x1990; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0991; CHECK-NEXT: ret992 %res = call <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, i32 -1)993 ret <vscale x 2 x i1> %res994}995 996; Ensure predicate based splice is promoted to use ZPRs.997define <vscale x 4 x i1> @splice_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b) #0 {998; CHECK-LABEL: splice_nxv4i1:999; CHECK: // %bb.0:1000; CHECK-NEXT: ptrue p2.s, vl11001; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x11002; CHECK-NEXT: mov z1.s, p0/z, #1 // =0x11003; CHECK-NEXT: rev p0.s, p2.s1004; CHECK-NEXT: splice z1.s, p0, z1.s, z0.s1005; CHECK-NEXT: ptrue p0.s1006; CHECK-NEXT: and z1.s, z1.s, #0x11007; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #01008; CHECK-NEXT: ret1009 %res = call <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, i32 -1)1010 ret <vscale x 4 x i1> %res1011}1012 1013; Ensure predicate based splice is promoted to use ZPRs.1014define <vscale x 8 x i1> @splice_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b) #0 {1015; CHECK-LABEL: splice_nxv8i1:1016; CHECK: // %bb.0:1017; CHECK-NEXT: ptrue p2.h, vl11018; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x11019; CHECK-NEXT: mov z1.h, p0/z, #1 // =0x11020; CHECK-NEXT: rev p0.h, p2.h1021; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h1022; CHECK-NEXT: ptrue p0.h1023; CHECK-NEXT: and z1.h, z1.h, #0x11024; CHECK-NEXT: cmpne p0.h, p0/z, z1.h, #01025; CHECK-NEXT: ret1026 %res = call <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, i32 -1)1027 ret <vscale x 8 x i1> %res1028}1029 1030; Ensure predicate based splice is promoted to use ZPRs.1031define <vscale x 16 x i1> @splice_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) #0 {1032; CHECK-LABEL: splice_nxv16i1:1033; CHECK: // %bb.0:1034; CHECK-NEXT: ptrue p2.b, vl11035; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x11036; CHECK-NEXT: mov z1.b, p0/z, #1 // =0x11037; CHECK-NEXT: rev p0.b, p2.b1038; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b1039; CHECK-NEXT: ptrue p0.b1040; CHECK-NEXT: and z1.b, z1.b, #0x11041; CHECK-NEXT: cmpne p0.b, p0/z, z1.b, #01042; CHECK-NEXT: ret1043 %res = call <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, i32 -1)1044 ret <vscale x 16 x i1> %res1045}1046 1047; Verify promote type legalisation works as expected.1048define <vscale x 2 x i8> @splice_nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) #0 {1049; CHECK-LABEL: splice_nxv2i8:1050; CHECK: // %bb.0:1051; CHECK-NEXT: ptrue p0.d, vl21052; CHECK-NEXT: rev p0.d, p0.d1053; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d1054; CHECK-NEXT: ret1055 %res = call <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -2)1056 ret <vscale x 2 x i8> %res1057}1058 1059; Verify splitvec type legalisation works as expected.1060define <vscale x 8 x i32> @splice_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {1061; CHECK-LABEL: splice_nxv8i32:1062; CHECK: // %bb.0:1063; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1064; CHECK-NEXT: addvl sp, sp, #-41065; CHECK-NEXT: rdvl x8, #21066; CHECK-NEXT: mov x9, sp1067; CHECK-NEXT: ptrue p0.s1068; CHECK-NEXT: add x8, x9, x81069; CHECK-NEXT: str z1, [sp, #1, mul vl]1070; CHECK-NEXT: mov x9, #-8 // =0xfffffffffffffff81071; CHECK-NEXT: str z0, [sp]1072; CHECK-NEXT: sub x10, x8, #321073; CHECK-NEXT: str z3, [sp, #3, mul vl]1074; CHECK-NEXT: str z2, [sp, #2, mul vl]1075; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2]1076; CHECK-NEXT: ldr z1, [x10, #1, mul vl]1077; CHECK-NEXT: addvl sp, sp, #41078; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1079; CHECK-NEXT: ret1080 %res = call <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -8)1081 ret <vscale x 8 x i32> %res1082}1083 1084; Verify splitvec type legalisation works as expected.1085define <vscale x 16 x float> @splice_nxv16f32_neg17(<vscale x 16 x float> %a, <vscale x 16 x float> %b) vscale_range(2,16) #0 {1086; CHECK-LABEL: splice_nxv16f32_neg17:1087; CHECK: // %bb.0:1088; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill1089; CHECK-NEXT: addvl sp, sp, #-81090; CHECK-NEXT: rdvl x8, #41091; CHECK-NEXT: mov w9, #68 // =0x441092; CHECK-NEXT: mov x10, sp1093; CHECK-NEXT: cmp x8, #681094; CHECK-NEXT: str z3, [sp, #3, mul vl]1095; CHECK-NEXT: csel x9, x8, x9, lo1096; CHECK-NEXT: add x8, x10, x81097; CHECK-NEXT: str z2, [sp, #2, mul vl]1098; CHECK-NEXT: str z1, [sp, #1, mul vl]1099; CHECK-NEXT: sub x8, x8, x91100; CHECK-NEXT: str z0, [sp]1101; CHECK-NEXT: str z7, [sp, #7, mul vl]1102; CHECK-NEXT: str z4, [sp, #4, mul vl]1103; CHECK-NEXT: str z5, [sp, #5, mul vl]1104; CHECK-NEXT: str z6, [sp, #6, mul vl]1105; CHECK-NEXT: ldr z0, [x8]1106; CHECK-NEXT: ldr z1, [x8, #1, mul vl]1107; CHECK-NEXT: ldr z2, [x8, #2, mul vl]1108; CHECK-NEXT: ldr z3, [x8, #3, mul vl]1109; CHECK-NEXT: addvl sp, sp, #81110; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload1111; CHECK-NEXT: ret1112 %res = call <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -17)1113 ret <vscale x 16 x float> %res1114}1115 1116declare <vscale x 2 x i1> @llvm.vector.splice.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)1117declare <vscale x 4 x i1> @llvm.vector.splice.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>, i32)1118declare <vscale x 8 x i1> @llvm.vector.splice.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>, i32)1119declare <vscale x 16 x i1> @llvm.vector.splice.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, i32)1120 1121declare <vscale x 2 x i8> @llvm.vector.splice.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, i32)1122declare <vscale x 16 x i8> @llvm.vector.splice.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, i32)1123declare <vscale x 8 x i16> @llvm.vector.splice.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)1124declare <vscale x 4 x i32> @llvm.vector.splice.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)1125declare <vscale x 8 x i32> @llvm.vector.splice.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, i32)1126declare <vscale x 2 x i64> @llvm.vector.splice.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)1127 1128declare <vscale x 2 x half> @llvm.vector.splice.nxv2f16(<vscale x 2 x half>, <vscale x 2 x half>, i32)1129declare <vscale x 4 x half> @llvm.vector.splice.nxv4f16(<vscale x 4 x half>, <vscale x 4 x half>, i32)1130declare <vscale x 8 x half> @llvm.vector.splice.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, i32)1131declare <vscale x 2 x float> @llvm.vector.splice.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, i32)1132declare <vscale x 4 x float> @llvm.vector.splice.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, i32)1133declare <vscale x 16 x float> @llvm.vector.splice.nxv16f32(<vscale x 16 x float>, <vscale x 16 x float>, i32)1134declare <vscale x 2 x double> @llvm.vector.splice.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, i32)1135 1136declare <vscale x 2 x bfloat> @llvm.vector.splice.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i32)1137declare <vscale x 4 x bfloat> @llvm.vector.splice.nxv4bf16(<vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i32)1138declare <vscale x 8 x bfloat> @llvm.vector.splice.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)1139 1140attributes #0 = { nounwind "target-features"="+sve" }1141