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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64"5 6; Check that an expanded vbsl(vneg(pre_cond), left, right) lowers to a VBSL7; during ISEL.8;9; Subtly different from a plain vector bit select: operand representing the10; condition has been negated (-v, not to be confused with bitwise_not(v)).11 12; Each vbsl_neg_cond_xxxx tests one of the 16 permutations of the operands.13 14define <4 x i32> @vbsl_neg_cond_0000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {15; CHECK-LABEL: vbsl_neg_cond_0000:16; CHECK: // %bb.0:17; CHECK-NEXT: neg v0.4s, v0.4s18; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b19; CHECK-NEXT: ret20 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond21 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>22 %left_bits_0 = and <4 x i32> %neg_cond, %left23 %right_bits_0 = and <4 x i32> %min_cond, %right24 %bsl0000 = or <4 x i32> %right_bits_0, %left_bits_025 ret <4 x i32> %bsl000026}27 28define <4 x i32> @vbsl_neg_cond_0001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {29; CHECK-LABEL: vbsl_neg_cond_0001:30; CHECK: // %bb.0:31; CHECK-NEXT: neg v0.4s, v0.4s32; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b33; CHECK-NEXT: ret34 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond35 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>36 %left_bits_1 = and <4 x i32> %left, %neg_cond37 %right_bits_0 = and <4 x i32> %min_cond, %right38 %bsl0001 = or <4 x i32> %right_bits_0, %left_bits_139 ret <4 x i32> %bsl000140}41 42define <4 x i32> @vbsl_neg_cond_0010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {43; CHECK-LABEL: vbsl_neg_cond_0010:44; CHECK: // %bb.0:45; CHECK-NEXT: neg v0.4s, v0.4s46; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b47; CHECK-NEXT: ret48 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond49 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>50 %left_bits_0 = and <4 x i32> %neg_cond, %left51 %right_bits_1 = and <4 x i32> %right, %min_cond52 %bsl0010 = or <4 x i32> %right_bits_1, %left_bits_053 ret <4 x i32> %bsl001054}55 56define <4 x i32> @vbsl_neg_cond_0011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {57; CHECK-LABEL: vbsl_neg_cond_0011:58; CHECK: // %bb.0:59; CHECK-NEXT: neg v0.4s, v0.4s60; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b61; CHECK-NEXT: ret62 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond63 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>64 %left_bits_1 = and <4 x i32> %left, %neg_cond65 %right_bits_1 = and <4 x i32> %right, %min_cond66 %bsl0011 = or <4 x i32> %right_bits_1, %left_bits_167 ret <4 x i32> %bsl001168}69 70define <4 x i32> @vbsl_neg_cond_0100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {71; CHECK-LABEL: vbsl_neg_cond_0100:72; CHECK: // %bb.0:73; CHECK-NEXT: neg v0.4s, v0.4s74; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b75; CHECK-NEXT: ret76 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond77 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>78 %left_bits_0 = and <4 x i32> %neg_cond, %left79 %right_bits_0 = and <4 x i32> %min_cond, %right80 %bsl0100 = or <4 x i32> %left_bits_0, %right_bits_081 ret <4 x i32> %bsl010082}83 84define <4 x i32> @vbsl_neg_cond_0101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {85; CHECK-LABEL: vbsl_neg_cond_0101:86; CHECK: // %bb.0:87; CHECK-NEXT: neg v0.4s, v0.4s88; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b89; CHECK-NEXT: ret90 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond91 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>92 %left_bits_0 = and <4 x i32> %neg_cond, %left93 %right_bits_1 = and <4 x i32> %right, %min_cond94 %bsl0101 = or <4 x i32> %left_bits_0, %right_bits_195 ret <4 x i32> %bsl010196}97 98define <4 x i32> @vbsl_neg_cond_0110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {99; CHECK-LABEL: vbsl_neg_cond_0110:100; CHECK: // %bb.0:101; CHECK-NEXT: neg v0.4s, v0.4s102; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b103; CHECK-NEXT: ret104 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond105 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>106 %left_bits_1 = and <4 x i32> %left, %neg_cond107 %right_bits_0 = and <4 x i32> %min_cond, %right108 %bsl0110 = or <4 x i32> %left_bits_1, %right_bits_0109 ret <4 x i32> %bsl0110110}111 112define <4 x i32> @vbsl_neg_cond_0111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {113; CHECK-LABEL: vbsl_neg_cond_0111:114; CHECK: // %bb.0:115; CHECK-NEXT: neg v0.4s, v0.4s116; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b117; CHECK-NEXT: ret118 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond119 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>120 %left_bits_1 = and <4 x i32> %left, %neg_cond121 %right_bits_1 = and <4 x i32> %right, %min_cond122 %bsl0111 = or <4 x i32> %left_bits_1, %right_bits_1123 ret <4 x i32> %bsl0111124}125 126define <4 x i32> @vbsl_neg_cond_1000(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {127; CHECK-LABEL: vbsl_neg_cond_1000:128; CHECK: // %bb.0:129; CHECK-NEXT: neg v0.4s, v0.4s130; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b131; CHECK-NEXT: ret132 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond133 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>134 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left135 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right136 %bsl1000 = or <4 x i32> %flip_cond_right_bits_0, %flip_cond_left_bits_0137 ret <4 x i32> %bsl1000138}139 140define <4 x i32> @vbsl_neg_cond_1001(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {141; CHECK-LABEL: vbsl_neg_cond_1001:142; CHECK: // %bb.0:143; CHECK-NEXT: neg v0.4s, v0.4s144; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b145; CHECK-NEXT: ret146 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond147 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>148 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond149 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right150 %bsl1001 = or <4 x i32> %flip_cond_right_bits_0, %flip_cond_left_bits_1151 ret <4 x i32> %bsl1001152}153 154define <4 x i32> @vbsl_neg_cond_1010(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {155; CHECK-LABEL: vbsl_neg_cond_1010:156; CHECK: // %bb.0:157; CHECK-NEXT: neg v0.4s, v0.4s158; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b159; CHECK-NEXT: ret160 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond161 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>162 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left163 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond164 %bsl1010 = or <4 x i32> %flip_cond_right_bits_1, %flip_cond_left_bits_0165 ret <4 x i32> %bsl1010166}167 168define <4 x i32> @vbsl_neg_cond_1011(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {169; CHECK-LABEL: vbsl_neg_cond_1011:170; CHECK: // %bb.0:171; CHECK-NEXT: neg v0.4s, v0.4s172; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b173; CHECK-NEXT: ret174 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond175 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>176 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond177 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond178 %bsl1011 = or <4 x i32> %flip_cond_right_bits_1, %flip_cond_left_bits_1179 ret <4 x i32> %bsl1011180}181 182define <4 x i32> @vbsl_neg_cond_1100(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {183; CHECK-LABEL: vbsl_neg_cond_1100:184; CHECK: // %bb.0:185; CHECK-NEXT: neg v0.4s, v0.4s186; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b187; CHECK-NEXT: ret188 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond189 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>190 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left191 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right192 %bsl1100 = or <4 x i32> %flip_cond_left_bits_0, %flip_cond_right_bits_0193 ret <4 x i32> %bsl1100194}195 196define <4 x i32> @vbsl_neg_cond_1101(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {197; CHECK-LABEL: vbsl_neg_cond_1101:198; CHECK: // %bb.0:199; CHECK-NEXT: neg v0.4s, v0.4s200; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b201; CHECK-NEXT: ret202 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond203 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>204 %flip_cond_left_bits_0 = and <4 x i32> %min_cond, %left205 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond206 %bsl1101 = or <4 x i32> %flip_cond_left_bits_0, %flip_cond_right_bits_1207 ret <4 x i32> %bsl1101208}209 210define <4 x i32> @vbsl_neg_cond_1110(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {211; CHECK-LABEL: vbsl_neg_cond_1110:212; CHECK: // %bb.0:213; CHECK-NEXT: neg v0.4s, v0.4s214; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b215; CHECK-NEXT: ret216 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond217 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>218 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond219 %flip_cond_right_bits_0 = and <4 x i32> %neg_cond, %right220 %bsl1110 = or <4 x i32> %flip_cond_left_bits_1, %flip_cond_right_bits_0221 ret <4 x i32> %bsl1110222}223 224define <4 x i32> @vbsl_neg_cond_1111(<4 x i32> %pre_cond, <4 x i32> %left, <4 x i32> %right) #0 {225; CHECK-LABEL: vbsl_neg_cond_1111:226; CHECK: // %bb.0:227; CHECK-NEXT: neg v0.4s, v0.4s228; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b229; CHECK-NEXT: ret230 %neg_cond = sub <4 x i32> zeroinitializer, %pre_cond231 %min_cond = add <4 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1>232 %flip_cond_left_bits_1 = and <4 x i32> %left, %min_cond233 %flip_cond_right_bits_1 = and <4 x i32> %right, %neg_cond234 %bsl1111 = or <4 x i32> %flip_cond_left_bits_1, %flip_cond_right_bits_1235 ret <4 x i32> %bsl1111236}237 238attributes #0 = { "target-features"="+neon" }239