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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {6; CHECK-LABEL: and8xi8:7; CHECK: // %bb.0:8; CHECK-NEXT: and v0.8b, v0.8b, v1.8b9; CHECK-NEXT: ret10 %tmp1 = and <8 x i8> %a, %b;11 ret <8 x i8> %tmp112}13 14define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {15; CHECK-LABEL: and16xi8:16; CHECK: // %bb.0:17; CHECK-NEXT: and v0.16b, v0.16b, v1.16b18; CHECK-NEXT: ret19 %tmp1 = and <16 x i8> %a, %b;20 ret <16 x i8> %tmp121}22 23 24define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {25; CHECK-LABEL: orr8xi8:26; CHECK: // %bb.0:27; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b28; CHECK-NEXT: ret29 %tmp1 = or <8 x i8> %a, %b;30 ret <8 x i8> %tmp131}32 33define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {34; CHECK-LABEL: orr16xi8:35; CHECK: // %bb.0:36; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b37; CHECK-NEXT: ret38 %tmp1 = or <16 x i8> %a, %b;39 ret <16 x i8> %tmp140}41 42 43define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {44; CHECK-LABEL: xor8xi8:45; CHECK: // %bb.0:46; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b47; CHECK-NEXT: ret48 %tmp1 = xor <8 x i8> %a, %b;49 ret <8 x i8> %tmp150}51 52define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {53; CHECK-LABEL: xor16xi8:54; CHECK: // %bb.0:55; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b56; CHECK-NEXT: ret57 %tmp1 = xor <16 x i8> %a, %b;58 ret <16 x i8> %tmp159}60 61define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {62; CHECK-SD-LABEL: bsl8xi8_const:63; CHECK-SD: // %bb.0:64; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff65; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b66; CHECK-SD-NEXT: ret67;68; CHECK-GI-LABEL: bsl8xi8_const:69; CHECK-GI: // %bb.0:70; CHECK-GI-NEXT: adrp x8, .LCPI6_071; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI6_0]72; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b73; CHECK-GI-NEXT: ret74 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 >75 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 >76 %tmp3 = or <8 x i8> %tmp1, %tmp277 ret <8 x i8> %tmp378}79 80define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {81; CHECK-SD-LABEL: bsl16xi8_const:82; CHECK-SD: // %bb.0:83; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff84; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b85; CHECK-SD-NEXT: ret86;87; CHECK-GI-LABEL: bsl16xi8_const:88; CHECK-GI: // %bb.0:89; CHECK-GI-NEXT: adrp x8, .LCPI7_090; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]91; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b92; CHECK-GI-NEXT: ret93 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 >94 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 >95 %tmp3 = or <16 x i8> %tmp1, %tmp296 ret <16 x i8> %tmp397}98 99define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {100; CHECK-LABEL: orn8xi8:101; CHECK: // %bb.0:102; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b103; CHECK-NEXT: ret104 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >105 %tmp2 = or <8 x i8> %a, %tmp1106 ret <8 x i8> %tmp2107}108 109define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {110; CHECK-LABEL: orn16xi8:111; CHECK: // %bb.0:112; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b113; CHECK-NEXT: ret114 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >115 %tmp2 = or <16 x i8> %a, %tmp1116 ret <16 x i8> %tmp2117}118 119define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {120; CHECK-LABEL: bic8xi8:121; CHECK: // %bb.0:122; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b123; CHECK-NEXT: ret124 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >125 %tmp2 = and <8 x i8> %a, %tmp1126 ret <8 x i8> %tmp2127}128 129define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {130; CHECK-LABEL: bic16xi8:131; CHECK: // %bb.0:132; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b133; CHECK-NEXT: ret134 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >135 %tmp2 = and <16 x i8> %a, %tmp1136 ret <16 x i8> %tmp2137}138 139define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {140; CHECK-SD-LABEL: orrimm2s_lsl0:141; CHECK-SD: // %bb.0:142; CHECK-SD-NEXT: orr v0.2s, #255143; CHECK-SD-NEXT: ret144;145; CHECK-GI-LABEL: orrimm2s_lsl0:146; CHECK-GI: // %bb.0:147; CHECK-GI-NEXT: movi d1, #0x0000ff000000ff148; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b149; CHECK-GI-NEXT: ret150 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>151 ret <2 x i32> %tmp1152}153 154define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {155; CHECK-SD-LABEL: orrimm2s_lsl8:156; CHECK-SD: // %bb.0:157; CHECK-SD-NEXT: orr v0.2s, #255, lsl #8158; CHECK-SD-NEXT: ret159;160; CHECK-GI-LABEL: orrimm2s_lsl8:161; CHECK-GI: // %bb.0:162; CHECK-GI-NEXT: movi d1, #0x00ff000000ff00163; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b164; CHECK-GI-NEXT: ret165 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>166 ret <2 x i32> %tmp1167}168 169define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {170; CHECK-SD-LABEL: orrimm2s_lsl16:171; CHECK-SD: // %bb.0:172; CHECK-SD-NEXT: orr v0.2s, #255, lsl #16173; CHECK-SD-NEXT: ret174;175; CHECK-GI-LABEL: orrimm2s_lsl16:176; CHECK-GI: // %bb.0:177; CHECK-GI-NEXT: movi d1, #0xff000000ff0000178; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b179; CHECK-GI-NEXT: ret180 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>181 ret <2 x i32> %tmp1182}183 184define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {185; CHECK-SD-LABEL: orrimm2s_lsl24:186; CHECK-SD: // %bb.0:187; CHECK-SD-NEXT: orr v0.2s, #255, lsl #24188; CHECK-SD-NEXT: ret189;190; CHECK-GI-LABEL: orrimm2s_lsl24:191; CHECK-GI: // %bb.0:192; CHECK-GI-NEXT: movi d1, #0xff000000ff000000193; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b194; CHECK-GI-NEXT: ret195 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>196 ret <2 x i32> %tmp1197}198 199define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {200; CHECK-SD-LABEL: orrimm4s_lsl0:201; CHECK-SD: // %bb.0:202; CHECK-SD-NEXT: orr v0.4s, #255203; CHECK-SD-NEXT: ret204;205; CHECK-GI-LABEL: orrimm4s_lsl0:206; CHECK-GI: // %bb.0:207; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff208; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b209; CHECK-GI-NEXT: ret210 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>211 ret <4 x i32> %tmp1212}213 214define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {215; CHECK-SD-LABEL: orrimm4s_lsl8:216; CHECK-SD: // %bb.0:217; CHECK-SD-NEXT: orr v0.4s, #255, lsl #8218; CHECK-SD-NEXT: ret219;220; CHECK-GI-LABEL: orrimm4s_lsl8:221; CHECK-GI: // %bb.0:222; CHECK-GI-NEXT: movi v1.2d, #0x00ff000000ff00223; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b224; CHECK-GI-NEXT: ret225 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>226 ret <4 x i32> %tmp1227}228 229define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {230; CHECK-SD-LABEL: orrimm4s_lsl16:231; CHECK-SD: // %bb.0:232; CHECK-SD-NEXT: orr v0.4s, #255, lsl #16233; CHECK-SD-NEXT: ret234;235; CHECK-GI-LABEL: orrimm4s_lsl16:236; CHECK-GI: // %bb.0:237; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff0000238; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b239; CHECK-GI-NEXT: ret240 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>241 ret <4 x i32> %tmp1242}243 244define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {245; CHECK-SD-LABEL: orrimm4s_lsl24:246; CHECK-SD: // %bb.0:247; CHECK-SD-NEXT: orr v0.4s, #255, lsl #24248; CHECK-SD-NEXT: ret249;250; CHECK-GI-LABEL: orrimm4s_lsl24:251; CHECK-GI: // %bb.0:252; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff000000253; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b254; CHECK-GI-NEXT: ret255 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>256 ret <4 x i32> %tmp1257}258 259define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {260; CHECK-SD-LABEL: orrimm4h_lsl0:261; CHECK-SD: // %bb.0:262; CHECK-SD-NEXT: orr v0.4h, #255263; CHECK-SD-NEXT: ret264;265; CHECK-GI-LABEL: orrimm4h_lsl0:266; CHECK-GI: // %bb.0:267; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff268; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b269; CHECK-GI-NEXT: ret270 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >271 ret <4 x i16> %tmp1272}273 274define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {275; CHECK-SD-LABEL: orrimm4h_lsl8:276; CHECK-SD: // %bb.0:277; CHECK-SD-NEXT: orr v0.4h, #255, lsl #8278; CHECK-SD-NEXT: ret279;280; CHECK-GI-LABEL: orrimm4h_lsl8:281; CHECK-GI: // %bb.0:282; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00283; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b284; CHECK-GI-NEXT: ret285 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >286 ret <4 x i16> %tmp1287}288 289define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {290; CHECK-SD-LABEL: orrimm8h_lsl0:291; CHECK-SD: // %bb.0:292; CHECK-SD-NEXT: orr v0.8h, #255293; CHECK-SD-NEXT: ret294;295; CHECK-GI-LABEL: orrimm8h_lsl0:296; CHECK-GI: // %bb.0:297; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff298; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b299; CHECK-GI-NEXT: ret300 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >301 ret <8 x i16> %tmp1302}303 304define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {305; CHECK-SD-LABEL: orrimm8h_lsl8:306; CHECK-SD: // %bb.0:307; CHECK-SD-NEXT: orr v0.8h, #255, lsl #8308; CHECK-SD-NEXT: ret309;310; CHECK-GI-LABEL: orrimm8h_lsl8:311; CHECK-GI: // %bb.0:312; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00313; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b314; CHECK-GI-NEXT: ret315 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >316 ret <8 x i16> %tmp1317}318 319define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {320; CHECK-SD-LABEL: bicimm2s_lsl0:321; CHECK-SD: // %bb.0:322; CHECK-SD-NEXT: bic v0.2s, #16323; CHECK-SD-NEXT: ret324;325; CHECK-GI-LABEL: bicimm2s_lsl0:326; CHECK-GI: // %bb.0:327; CHECK-GI-NEXT: mvni v1.2s, #16328; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b329; CHECK-GI-NEXT: ret330 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >331 ret <2 x i32> %tmp1332}333 334define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {335; CHECK-SD-LABEL: bicimm2s_lsl8:336; CHECK-SD: // %bb.0:337; CHECK-SD-NEXT: bic v0.2s, #16, lsl #8338; CHECK-SD-NEXT: ret339;340; CHECK-GI-LABEL: bicimm2s_lsl8:341; CHECK-GI: // %bb.0:342; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #8343; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b344; CHECK-GI-NEXT: ret345 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >346 ret <2 x i32> %tmp1347}348 349define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {350; CHECK-SD-LABEL: bicimm2s_lsl16:351; CHECK-SD: // %bb.0:352; CHECK-SD-NEXT: bic v0.2s, #16, lsl #16353; CHECK-SD-NEXT: ret354;355; CHECK-GI-LABEL: bicimm2s_lsl16:356; CHECK-GI: // %bb.0:357; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #16358; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b359; CHECK-GI-NEXT: ret360 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >361 ret <2 x i32> %tmp1362}363 364define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {365; CHECK-SD-LABEL: bicimm2s_lsl124:366; CHECK-SD: // %bb.0:367; CHECK-SD-NEXT: bic v0.2s, #16, lsl #24368; CHECK-SD-NEXT: ret369;370; CHECK-GI-LABEL: bicimm2s_lsl124:371; CHECK-GI: // %bb.0:372; CHECK-GI-NEXT: mvni v1.2s, #16, lsl #24373; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b374; CHECK-GI-NEXT: ret375 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>376 ret <2 x i32> %tmp1377}378 379define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {380; CHECK-SD-LABEL: bicimm4s_lsl0:381; CHECK-SD: // %bb.0:382; CHECK-SD-NEXT: bic v0.4s, #16383; CHECK-SD-NEXT: ret384;385; CHECK-GI-LABEL: bicimm4s_lsl0:386; CHECK-GI: // %bb.0:387; CHECK-GI-NEXT: mvni v1.4s, #16388; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b389; CHECK-GI-NEXT: ret390 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >391 ret <4 x i32> %tmp1392}393 394define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {395; CHECK-SD-LABEL: bicimm4s_lsl8:396; CHECK-SD: // %bb.0:397; CHECK-SD-NEXT: bic v0.4s, #16, lsl #8398; CHECK-SD-NEXT: ret399;400; CHECK-GI-LABEL: bicimm4s_lsl8:401; CHECK-GI: // %bb.0:402; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #8403; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b404; CHECK-GI-NEXT: ret405 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >406 ret <4 x i32> %tmp1407}408 409define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {410; CHECK-SD-LABEL: bicimm4s_lsl16:411; CHECK-SD: // %bb.0:412; CHECK-SD-NEXT: bic v0.4s, #16, lsl #16413; CHECK-SD-NEXT: ret414;415; CHECK-GI-LABEL: bicimm4s_lsl16:416; CHECK-GI: // %bb.0:417; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #16418; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b419; CHECK-GI-NEXT: ret420 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >421 ret <4 x i32> %tmp1422}423 424define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {425; CHECK-SD-LABEL: bicimm4s_lsl124:426; CHECK-SD: // %bb.0:427; CHECK-SD-NEXT: bic v0.4s, #16, lsl #24428; CHECK-SD-NEXT: ret429;430; CHECK-GI-LABEL: bicimm4s_lsl124:431; CHECK-GI: // %bb.0:432; CHECK-GI-NEXT: mvni v1.4s, #16, lsl #24433; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b434; CHECK-GI-NEXT: ret435 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>436 ret <4 x i32> %tmp1437}438 439define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {440; CHECK-SD-LABEL: bicimm4h_lsl0_a:441; CHECK-SD: // %bb.0:442; CHECK-SD-NEXT: bic v0.4h, #16443; CHECK-SD-NEXT: ret444;445; CHECK-GI-LABEL: bicimm4h_lsl0_a:446; CHECK-GI: // %bb.0:447; CHECK-GI-NEXT: mvni v1.4h, #16448; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b449; CHECK-GI-NEXT: ret450 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >451 ret <4 x i16> %tmp1452}453 454define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {455; CHECK-SD-LABEL: bicimm4h_lsl0_b:456; CHECK-SD: // %bb.0:457; CHECK-SD-NEXT: bic v0.4h, #255458; CHECK-SD-NEXT: ret459;460; CHECK-GI-LABEL: bicimm4h_lsl0_b:461; CHECK-GI: // %bb.0:462; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff00463; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b464; CHECK-GI-NEXT: ret465 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >466 ret <4 x i16> %tmp1467}468 469define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {470; CHECK-SD-LABEL: bicimm4h_lsl8_a:471; CHECK-SD: // %bb.0:472; CHECK-SD-NEXT: bic v0.4h, #16, lsl #8473; CHECK-SD-NEXT: ret474;475; CHECK-GI-LABEL: bicimm4h_lsl8_a:476; CHECK-GI: // %bb.0:477; CHECK-GI-NEXT: mvni v1.4h, #16, lsl #8478; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b479; CHECK-GI-NEXT: ret480 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>481 ret <4 x i16> %tmp1482}483 484define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {485; CHECK-SD-LABEL: bicimm4h_lsl8_b:486; CHECK-SD: // %bb.0:487; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8488; CHECK-SD-NEXT: ret489;490; CHECK-GI-LABEL: bicimm4h_lsl8_b:491; CHECK-GI: // %bb.0:492; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff493; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b494; CHECK-GI-NEXT: ret495 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>496 ret <4 x i16> %tmp1497}498 499define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {500; CHECK-SD-LABEL: bicimm8h_lsl0_a:501; CHECK-SD: // %bb.0:502; CHECK-SD-NEXT: bic v0.8h, #16503; CHECK-SD-NEXT: ret504;505; CHECK-GI-LABEL: bicimm8h_lsl0_a:506; CHECK-GI: // %bb.0:507; CHECK-GI-NEXT: mvni v1.8h, #16508; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b509; CHECK-GI-NEXT: ret510 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,511 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >512 ret <8 x i16> %tmp1513}514 515define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {516; CHECK-SD-LABEL: bicimm8h_lsl0_b:517; CHECK-SD: // %bb.0:518; CHECK-SD-NEXT: bic v0.8h, #255519; CHECK-SD-NEXT: ret520;521; CHECK-GI-LABEL: bicimm8h_lsl0_b:522; CHECK-GI: // %bb.0:523; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff00524; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b525; CHECK-GI-NEXT: ret526 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >527 ret <8 x i16> %tmp1528}529 530define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {531; CHECK-SD-LABEL: bicimm8h_lsl8_a:532; CHECK-SD: // %bb.0:533; CHECK-SD-NEXT: bic v0.8h, #16, lsl #8534; CHECK-SD-NEXT: ret535;536; CHECK-GI-LABEL: bicimm8h_lsl8_a:537; CHECK-GI: // %bb.0:538; CHECK-GI-NEXT: mvni v1.8h, #16, lsl #8539; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b540; CHECK-GI-NEXT: ret541 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,542 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>543 ret <8 x i16> %tmp1544}545 546define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {547; CHECK-SD-LABEL: bicimm8h_lsl8_b:548; CHECK-SD: // %bb.0:549; CHECK-SD-NEXT: bic v0.8h, #255, lsl #8550; CHECK-SD-NEXT: ret551;552; CHECK-GI-LABEL: bicimm8h_lsl8_b:553; CHECK-GI: // %bb.0:554; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff555; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b556; CHECK-GI-NEXT: ret557 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>558 ret <8 x i16> %tmp1559}560 561define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {562; CHECK-LABEL: and2xi32:563; CHECK: // %bb.0:564; CHECK-NEXT: and v0.8b, v0.8b, v1.8b565; CHECK-NEXT: ret566 %tmp1 = and <2 x i32> %a, %b;567 ret <2 x i32> %tmp1568}569 570define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {571; CHECK-LABEL: and4xi16:572; CHECK: // %bb.0:573; CHECK-NEXT: and v0.8b, v0.8b, v1.8b574; CHECK-NEXT: ret575 %tmp1 = and <4 x i16> %a, %b;576 ret <4 x i16> %tmp1577}578 579define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {580; CHECK-SD-LABEL: and1xi64:581; CHECK-SD: // %bb.0:582; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b583; CHECK-SD-NEXT: ret584;585; CHECK-GI-LABEL: and1xi64:586; CHECK-GI: // %bb.0:587; CHECK-GI-NEXT: fmov x8, d0588; CHECK-GI-NEXT: fmov x9, d1589; CHECK-GI-NEXT: and x8, x8, x9590; CHECK-GI-NEXT: fmov d0, x8591; CHECK-GI-NEXT: ret592 %tmp1 = and <1 x i64> %a, %b;593 ret <1 x i64> %tmp1594}595 596define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {597; CHECK-LABEL: and4xi32:598; CHECK: // %bb.0:599; CHECK-NEXT: and v0.16b, v0.16b, v1.16b600; CHECK-NEXT: ret601 %tmp1 = and <4 x i32> %a, %b;602 ret <4 x i32> %tmp1603}604 605define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {606; CHECK-LABEL: and8xi16:607; CHECK: // %bb.0:608; CHECK-NEXT: and v0.16b, v0.16b, v1.16b609; CHECK-NEXT: ret610 %tmp1 = and <8 x i16> %a, %b;611 ret <8 x i16> %tmp1612}613 614define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {615; CHECK-LABEL: and2xi64:616; CHECK: // %bb.0:617; CHECK-NEXT: and v0.16b, v0.16b, v1.16b618; CHECK-NEXT: ret619 %tmp1 = and <2 x i64> %a, %b;620 ret <2 x i64> %tmp1621}622 623define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {624; CHECK-LABEL: orr2xi32:625; CHECK: // %bb.0:626; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b627; CHECK-NEXT: ret628 %tmp1 = or <2 x i32> %a, %b;629 ret <2 x i32> %tmp1630}631 632define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {633; CHECK-LABEL: orr4xi16:634; CHECK: // %bb.0:635; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b636; CHECK-NEXT: ret637 %tmp1 = or <4 x i16> %a, %b;638 ret <4 x i16> %tmp1639}640 641define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {642; CHECK-SD-LABEL: orr1xi64:643; CHECK-SD: // %bb.0:644; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b645; CHECK-SD-NEXT: ret646;647; CHECK-GI-LABEL: orr1xi64:648; CHECK-GI: // %bb.0:649; CHECK-GI-NEXT: fmov x8, d0650; CHECK-GI-NEXT: fmov x9, d1651; CHECK-GI-NEXT: orr x8, x8, x9652; CHECK-GI-NEXT: fmov d0, x8653; CHECK-GI-NEXT: ret654 %tmp1 = or <1 x i64> %a, %b;655 ret <1 x i64> %tmp1656}657 658define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {659; CHECK-LABEL: orr4xi32:660; CHECK: // %bb.0:661; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b662; CHECK-NEXT: ret663 %tmp1 = or <4 x i32> %a, %b;664 ret <4 x i32> %tmp1665}666 667define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {668; CHECK-LABEL: orr8xi16:669; CHECK: // %bb.0:670; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b671; CHECK-NEXT: ret672 %tmp1 = or <8 x i16> %a, %b;673 ret <8 x i16> %tmp1674}675 676define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {677; CHECK-LABEL: orr2xi64:678; CHECK: // %bb.0:679; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b680; CHECK-NEXT: ret681 %tmp1 = or <2 x i64> %a, %b;682 ret <2 x i64> %tmp1683}684 685define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {686; CHECK-LABEL: eor2xi32:687; CHECK: // %bb.0:688; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b689; CHECK-NEXT: ret690 %tmp1 = xor <2 x i32> %a, %b;691 ret <2 x i32> %tmp1692}693 694define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {695; CHECK-LABEL: eor4xi16:696; CHECK: // %bb.0:697; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b698; CHECK-NEXT: ret699 %tmp1 = xor <4 x i16> %a, %b;700 ret <4 x i16> %tmp1701}702 703define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {704; CHECK-SD-LABEL: eor1xi64:705; CHECK-SD: // %bb.0:706; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b707; CHECK-SD-NEXT: ret708;709; CHECK-GI-LABEL: eor1xi64:710; CHECK-GI: // %bb.0:711; CHECK-GI-NEXT: fmov x8, d0712; CHECK-GI-NEXT: fmov x9, d1713; CHECK-GI-NEXT: eor x8, x8, x9714; CHECK-GI-NEXT: fmov d0, x8715; CHECK-GI-NEXT: ret716 %tmp1 = xor <1 x i64> %a, %b;717 ret <1 x i64> %tmp1718}719 720define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {721; CHECK-LABEL: eor4xi32:722; CHECK: // %bb.0:723; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b724; CHECK-NEXT: ret725 %tmp1 = xor <4 x i32> %a, %b;726 ret <4 x i32> %tmp1727}728 729define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {730; CHECK-LABEL: eor8xi16:731; CHECK: // %bb.0:732; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b733; CHECK-NEXT: ret734 %tmp1 = xor <8 x i16> %a, %b;735 ret <8 x i16> %tmp1736}737 738define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {739; CHECK-LABEL: eor2xi64:740; CHECK: // %bb.0:741; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b742; CHECK-NEXT: ret743 %tmp1 = xor <2 x i64> %a, %b;744 ret <2 x i64> %tmp1745}746 747 748define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {749; CHECK-LABEL: bic2xi32:750; CHECK: // %bb.0:751; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b752; CHECK-NEXT: ret753 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >754 %tmp2 = and <2 x i32> %a, %tmp1755 ret <2 x i32> %tmp2756}757 758define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {759; CHECK-LABEL: bic4xi16:760; CHECK: // %bb.0:761; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b762; CHECK-NEXT: ret763 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >764 %tmp2 = and <4 x i16> %a, %tmp1765 ret <4 x i16> %tmp2766}767 768define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {769; CHECK-SD-LABEL: bic1xi64:770; CHECK-SD: // %bb.0:771; CHECK-SD-NEXT: bic v0.8b, v0.8b, v1.8b772; CHECK-SD-NEXT: ret773;774; CHECK-GI-LABEL: bic1xi64:775; CHECK-GI: // %bb.0:776; CHECK-GI-NEXT: fmov x8, d1777; CHECK-GI-NEXT: fmov x9, d0778; CHECK-GI-NEXT: bic x8, x9, x8779; CHECK-GI-NEXT: fmov d0, x8780; CHECK-GI-NEXT: ret781 %tmp1 = xor <1 x i64> %b, < i64 -1>782 %tmp2 = and <1 x i64> %a, %tmp1783 ret <1 x i64> %tmp2784}785 786define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {787; CHECK-LABEL: bic4xi32:788; CHECK: // %bb.0:789; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b790; CHECK-NEXT: ret791 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>792 %tmp2 = and <4 x i32> %a, %tmp1793 ret <4 x i32> %tmp2794}795 796define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {797; CHECK-LABEL: bic8xi16:798; CHECK: // %bb.0:799; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b800; CHECK-NEXT: ret801 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >802 %tmp2 = and <8 x i16> %a, %tmp1803 ret <8 x i16> %tmp2804}805 806define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {807; CHECK-LABEL: bic2xi64:808; CHECK: // %bb.0:809; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b810; CHECK-NEXT: ret811 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>812 %tmp2 = and <2 x i64> %a, %tmp1813 ret <2 x i64> %tmp2814}815 816define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {817; CHECK-LABEL: orn2xi32:818; CHECK: // %bb.0:819; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b820; CHECK-NEXT: ret821 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >822 %tmp2 = or <2 x i32> %a, %tmp1823 ret <2 x i32> %tmp2824}825 826define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {827; CHECK-LABEL: orn4xi16:828; CHECK: // %bb.0:829; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b830; CHECK-NEXT: ret831 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >832 %tmp2 = or <4 x i16> %a, %tmp1833 ret <4 x i16> %tmp2834}835 836define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {837; CHECK-SD-LABEL: orn1xi64:838; CHECK-SD: // %bb.0:839; CHECK-SD-NEXT: orn v0.8b, v0.8b, v1.8b840; CHECK-SD-NEXT: ret841;842; CHECK-GI-LABEL: orn1xi64:843; CHECK-GI: // %bb.0:844; CHECK-GI-NEXT: fmov x8, d1845; CHECK-GI-NEXT: fmov x9, d0846; CHECK-GI-NEXT: orn x8, x9, x8847; CHECK-GI-NEXT: fmov d0, x8848; CHECK-GI-NEXT: ret849 %tmp1 = xor <1 x i64> %b, < i64 -1>850 %tmp2 = or <1 x i64> %a, %tmp1851 ret <1 x i64> %tmp2852}853 854define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {855; CHECK-LABEL: orn4xi32:856; CHECK: // %bb.0:857; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b858; CHECK-NEXT: ret859 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>860 %tmp2 = or <4 x i32> %a, %tmp1861 ret <4 x i32> %tmp2862}863 864define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {865; CHECK-LABEL: orn8xi16:866; CHECK: // %bb.0:867; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b868; CHECK-NEXT: ret869 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >870 %tmp2 = or <8 x i16> %a, %tmp1871 ret <8 x i16> %tmp2872}873 874define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {875; CHECK-LABEL: orn2xi64:876; CHECK: // %bb.0:877; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b878; CHECK-NEXT: ret879 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>880 %tmp2 = or <2 x i64> %a, %tmp1881 ret <2 x i64> %tmp2882}883 884define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {885; CHECK-SD-LABEL: bsl2xi32_const:886; CHECK-SD: // %bb.0:887; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0888; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1889; CHECK-SD-NEXT: mov v0.s[1], v1.s[1]890; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0891; CHECK-SD-NEXT: ret892;893; CHECK-GI-LABEL: bsl2xi32_const:894; CHECK-GI: // %bb.0:895; CHECK-GI-NEXT: adrp x8, .LCPI70_0896; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI70_0]897; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b898; CHECK-GI-NEXT: ret899 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 >900 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 >901 %tmp3 = or <2 x i32> %tmp1, %tmp2902 ret <2 x i32> %tmp3903}904 905 906define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {907; CHECK-SD-LABEL: bsl4xi16_const:908; CHECK-SD: // %bb.0:909; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff910; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b911; CHECK-SD-NEXT: ret912;913; CHECK-GI-LABEL: bsl4xi16_const:914; CHECK-GI: // %bb.0:915; CHECK-GI-NEXT: adrp x8, .LCPI71_0916; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI71_0]917; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b918; CHECK-GI-NEXT: ret919 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 >920 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 >921 %tmp3 = or <4 x i16> %tmp1, %tmp2922 ret <4 x i16> %tmp3923}924 925define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {926; CHECK-SD-LABEL: bsl1xi64_const:927; CHECK-SD: // %bb.0:928; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0929; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1930; CHECK-SD-NEXT: mov v0.b[0], v1.b[0]931; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0932; CHECK-SD-NEXT: ret933;934; CHECK-GI-LABEL: bsl1xi64_const:935; CHECK-GI: // %bb.0:936; CHECK-GI-NEXT: fmov x8, d0937; CHECK-GI-NEXT: fmov x9, d1938; CHECK-GI-NEXT: and x8, x8, #0xffffffffffffff00939; CHECK-GI-NEXT: and x9, x9, #0xff940; CHECK-GI-NEXT: orr x8, x8, x9941; CHECK-GI-NEXT: fmov d0, x8942; CHECK-GI-NEXT: ret943 %tmp1 = and <1 x i64> %a, < i64 -256 >944 %tmp2 = and <1 x i64> %b, < i64 255 >945 %tmp3 = or <1 x i64> %tmp1, %tmp2946 ret <1 x i64> %tmp3947}948 949define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {950; CHECK-SD-LABEL: bsl4xi32_const:951; CHECK-SD: // %bb.0:952; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff953; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b954; CHECK-SD-NEXT: ret955;956; CHECK-GI-LABEL: bsl4xi32_const:957; CHECK-GI: // %bb.0:958; CHECK-GI-NEXT: adrp x8, .LCPI73_0959; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI73_0]960; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b961; CHECK-GI-NEXT: ret962 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 >963 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 >964 %tmp3 = or <4 x i32> %tmp1, %tmp2965 ret <4 x i32> %tmp3966}967 968define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {969; CHECK-SD-LABEL: bsl8xi16_const:970; CHECK-SD: // %bb.0:971; CHECK-SD-NEXT: movi v2.2d, #0x000000ffffffff972; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b973; CHECK-SD-NEXT: ret974;975; CHECK-GI-LABEL: bsl8xi16_const:976; CHECK-GI: // %bb.0:977; CHECK-GI-NEXT: adrp x8, .LCPI74_0978; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI74_0]979; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b980; CHECK-GI-NEXT: ret981 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 >982 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 >983 %tmp3 = or <8 x i16> %tmp1, %tmp2984 ret <8 x i16> %tmp3985}986 987define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {988; CHECK-SD-LABEL: bsl2xi64_const:989; CHECK-SD: // %bb.0:990; CHECK-SD-NEXT: mov v0.d[1], v1.d[1]991; CHECK-SD-NEXT: ret992;993; CHECK-GI-LABEL: bsl2xi64_const:994; CHECK-GI: // %bb.0:995; CHECK-GI-NEXT: adrp x8, .LCPI75_0996; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI75_0]997; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b998; CHECK-GI-NEXT: ret999 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 >1000 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 >1001 %tmp3 = or <2 x i64> %tmp1, %tmp21002 ret <2 x i64> %tmp31003}1004 1005 1006define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {1007; CHECK-LABEL: bsl8xi8:1008; CHECK: // %bb.0:1009; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b1010; CHECK-NEXT: ret1011 %1 = and <8 x i8> %v1, %v21012 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1013 %3 = and <8 x i8> %2, %v31014 %4 = or <8 x i8> %1, %31015 ret <8 x i8> %41016}1017 1018define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {1019; CHECK-LABEL: bsl4xi16:1020; CHECK: // %bb.0:1021; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b1022; CHECK-NEXT: ret1023 %1 = and <4 x i16> %v1, %v21024 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>1025 %3 = and <4 x i16> %2, %v31026 %4 = or <4 x i16> %1, %31027 ret <4 x i16> %41028}1029 1030define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {1031; CHECK-LABEL: bsl2xi32:1032; CHECK: // %bb.0:1033; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b1034; CHECK-NEXT: ret1035 %1 = and <2 x i32> %v1, %v21036 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>1037 %3 = and <2 x i32> %2, %v31038 %4 = or <2 x i32> %1, %31039 ret <2 x i32> %41040}1041 1042define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {1043; CHECK-SD-LABEL: bsl1xi64:1044; CHECK-SD: // %bb.0:1045; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b1046; CHECK-SD-NEXT: ret1047;1048; CHECK-GI-LABEL: bsl1xi64:1049; CHECK-GI: // %bb.0:1050; CHECK-GI-NEXT: fmov x8, d01051; CHECK-GI-NEXT: fmov x9, d11052; CHECK-GI-NEXT: fmov x10, d21053; CHECK-GI-NEXT: and x9, x8, x91054; CHECK-GI-NEXT: bic x8, x10, x81055; CHECK-GI-NEXT: orr x8, x9, x81056; CHECK-GI-NEXT: fmov d0, x81057; CHECK-GI-NEXT: ret1058 %1 = and <1 x i64> %v1, %v21059 %2 = xor <1 x i64> %v1, <i64 -1>1060 %3 = and <1 x i64> %2, %v31061 %4 = or <1 x i64> %1, %31062 ret <1 x i64> %41063}1064 1065define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {1066; CHECK-LABEL: bsl16xi8:1067; CHECK: // %bb.0:1068; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b1069; CHECK-NEXT: ret1070 %1 = and <16 x i8> %v1, %v21071 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1072 %3 = and <16 x i8> %2, %v31073 %4 = or <16 x i8> %1, %31074 ret <16 x i8> %41075}1076 1077define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {1078; CHECK-LABEL: bsl8xi16:1079; CHECK: // %bb.0:1080; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b1081; CHECK-NEXT: ret1082 %1 = and <8 x i16> %v1, %v21083 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>1084 %3 = and <8 x i16> %2, %v31085 %4 = or <8 x i16> %1, %31086 ret <8 x i16> %41087}1088 1089define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {1090; CHECK-LABEL: bsl4xi32:1091; CHECK: // %bb.0:1092; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b1093; CHECK-NEXT: ret1094 %1 = and <4 x i32> %v1, %v21095 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>1096 %3 = and <4 x i32> %2, %v31097 %4 = or <4 x i32> %1, %31098 ret <4 x i32> %41099}1100 1101define <8 x i8> @vselect_constant_cond_zero_v8i8(<8 x i8> %a) {1102; CHECK-SD-LABEL: vselect_constant_cond_zero_v8i8:1103; CHECK-SD: // %bb.0:1104; CHECK-SD-NEXT: movi d1, #0x00000000ff00ff1105; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b1106; CHECK-SD-NEXT: ret1107;1108; CHECK-GI-LABEL: vselect_constant_cond_zero_v8i8:1109; CHECK-GI: // %bb.0:1110; CHECK-GI-NEXT: adrp x8, .LCPI83_01111; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI83_0]1112; CHECK-GI-NEXT: shl v1.8b, v1.8b, #71113; CHECK-GI-NEXT: cmlt v1.8b, v1.8b, #01114; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1115; CHECK-GI-NEXT: ret1116 %b = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> zeroinitializer1117 ret <8 x i8> %b1118}1119 1120define <4 x i16> @vselect_constant_cond_zero_v4i16(<4 x i16> %a) {1121; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i16:1122; CHECK-SD: // %bb.0:1123; CHECK-SD-NEXT: movi d1, #0xffff00000000ffff1124; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b1125; CHECK-SD-NEXT: ret1126;1127; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i16:1128; CHECK-GI: // %bb.0:1129; CHECK-GI-NEXT: mov w8, #1 // =0x11130; CHECK-GI-NEXT: mov w9, #0 // =0x01131; CHECK-GI-NEXT: fmov s1, w81132; CHECK-GI-NEXT: mov v1.h[1], w91133; CHECK-GI-NEXT: mov v1.h[2], w91134; CHECK-GI-NEXT: mov v1.h[3], w81135; CHECK-GI-NEXT: shl v1.4h, v1.4h, #151136; CHECK-GI-NEXT: cmlt v1.4h, v1.4h, #01137; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1138; CHECK-GI-NEXT: ret1139 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> zeroinitializer1140 ret <4 x i16> %b1141}1142 1143define <4 x i32> @vselect_constant_cond_zero_v4i32(<4 x i32> %a) {1144; CHECK-SD-LABEL: vselect_constant_cond_zero_v4i32:1145; CHECK-SD: // %bb.0:1146; CHECK-SD-NEXT: adrp x8, .LCPI85_01147; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI85_0]1148; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b1149; CHECK-SD-NEXT: ret1150;1151; CHECK-GI-LABEL: vselect_constant_cond_zero_v4i32:1152; CHECK-GI: // %bb.0:1153; CHECK-GI-NEXT: mov w8, #1 // =0x11154; CHECK-GI-NEXT: mov w9, #0 // =0x01155; CHECK-GI-NEXT: fmov s1, w81156; CHECK-GI-NEXT: mov v1.s[1], w91157; CHECK-GI-NEXT: mov v1.s[2], w91158; CHECK-GI-NEXT: mov v1.s[3], w81159; CHECK-GI-NEXT: shl v1.4s, v1.4s, #311160; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #01161; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1162; CHECK-GI-NEXT: ret1163 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> zeroinitializer1164 ret <4 x i32> %b1165}1166 1167define <8 x i8> @vselect_constant_cond_v8i8(<8 x i8> %a, <8 x i8> %b) {1168; CHECK-SD-LABEL: vselect_constant_cond_v8i8:1169; CHECK-SD: // %bb.0:1170; CHECK-SD-NEXT: movi d2, #0x00000000ff00ff1171; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1172; CHECK-SD-NEXT: ret1173;1174; CHECK-GI-LABEL: vselect_constant_cond_v8i8:1175; CHECK-GI: // %bb.0:1176; CHECK-GI-NEXT: adrp x8, .LCPI86_01177; CHECK-GI-NEXT: ldr d2, [x8, :lo12:.LCPI86_0]1178; CHECK-GI-NEXT: shl v2.8b, v2.8b, #71179; CHECK-GI-NEXT: cmlt v2.8b, v2.8b, #01180; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b1181; CHECK-GI-NEXT: ret1182 %c = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> %b1183 ret <8 x i8> %c1184}1185 1186define <4 x i16> @vselect_constant_cond_v4i16(<4 x i16> %a, <4 x i16> %b) {1187; CHECK-SD-LABEL: vselect_constant_cond_v4i16:1188; CHECK-SD: // %bb.0:1189; CHECK-SD-NEXT: movi d2, #0xffff00000000ffff1190; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b1191; CHECK-SD-NEXT: ret1192;1193; CHECK-GI-LABEL: vselect_constant_cond_v4i16:1194; CHECK-GI: // %bb.0:1195; CHECK-GI-NEXT: mov w8, #1 // =0x11196; CHECK-GI-NEXT: mov w9, #0 // =0x01197; CHECK-GI-NEXT: fmov s2, w81198; CHECK-GI-NEXT: mov v2.h[1], w91199; CHECK-GI-NEXT: mov v2.h[2], w91200; CHECK-GI-NEXT: mov v2.h[3], w81201; CHECK-GI-NEXT: shl v2.4h, v2.4h, #151202; CHECK-GI-NEXT: cmlt v2.4h, v2.4h, #01203; CHECK-GI-NEXT: bif v0.8b, v1.8b, v2.8b1204; CHECK-GI-NEXT: ret1205 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i16> %a, <4 x i16> %b1206 ret <4 x i16> %c1207}1208 1209define <4 x i32> @vselect_constant_cond_v4i32(<4 x i32> %a, <4 x i32> %b) {1210; CHECK-SD-LABEL: vselect_constant_cond_v4i32:1211; CHECK-SD: // %bb.0:1212; CHECK-SD-NEXT: adrp x8, .LCPI88_01213; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI88_0]1214; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b1215; CHECK-SD-NEXT: ret1216;1217; CHECK-GI-LABEL: vselect_constant_cond_v4i32:1218; CHECK-GI: // %bb.0:1219; CHECK-GI-NEXT: mov w8, #1 // =0x11220; CHECK-GI-NEXT: mov w9, #0 // =0x01221; CHECK-GI-NEXT: fmov s2, w81222; CHECK-GI-NEXT: mov v2.s[1], w91223; CHECK-GI-NEXT: mov v2.s[2], w91224; CHECK-GI-NEXT: mov v2.s[3], w81225; CHECK-GI-NEXT: shl v2.4s, v2.4s, #311226; CHECK-GI-NEXT: cmlt v2.4s, v2.4s, #01227; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b1228; CHECK-GI-NEXT: ret1229 %c = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x i32> %a, <4 x i32> %b1230 ret <4 x i32> %c1231}1232 1233; CHECK-SD: .byte 01234; CHECK-SD: .byte 81235; CHECK-SD: .byte 21236; CHECK-SD: .byte 91237; CHECK-SD: .byte 41238; CHECK-SD: .byte 51239; CHECK-SD: .byte 61240; CHECK-SD: .byte 71241define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {1242; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8:1243; CHECK-SD: // %bb.0:1244; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01245; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11246; CHECK-SD-NEXT: adrp x8, .LCPI89_01247; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1248; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]1249; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b1250; CHECK-SD-NEXT: ret1251;1252; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8:1253; CHECK-GI: // %bb.0:1254; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01255; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11256; CHECK-GI-NEXT: adrp x8, .LCPI89_01257; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]1258; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI89_0]1259; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b1260; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q01261; CHECK-GI-NEXT: ret1262 %c = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>1263 ret <8 x i8> %c1264}1265 1266define <8 x i8> @vselect_equivalent_shuffle_v8i8_zero(<8 x i8> %a) {1267; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zero:1268; CHECK-SD: // %bb.0:1269; CHECK-SD-NEXT: movi d1, #0xffffffff00ff00ff1270; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b1271; CHECK-SD-NEXT: ret1272;1273; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zero:1274; CHECK-GI: // %bb.0:1275; CHECK-GI-NEXT: movi v1.2d, #00000000000000001276; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01277; CHECK-GI-NEXT: adrp x8, .LCPI90_01278; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]1279; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI90_0]1280; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b1281; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q01282; CHECK-GI-NEXT: ret1283 %c = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>1284 ret <8 x i8> %c1285}1286 1287; CHECK-SD-LABEL: .LCPI91_0:1288; CHECK-SD-NEXT: .byte 01289; CHECK-SD-NEXT: .byte 2551290; CHECK-SD-NEXT: .byte 21291; CHECK-SD-NEXT: .byte 2551292; CHECK-SD-NEXT: .byte 41293; CHECK-SD-NEXT: .byte 51294; CHECK-SD-NEXT: .byte 61295; CHECK-SD-NEXT: .byte 71296define <8 x i8> @vselect_equivalent_shuffle_v8i8_zeroswap(<8 x i8> %a) {1297; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:1298; CHECK-SD: // %bb.0:1299; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01300; CHECK-SD-NEXT: adrp x8, .LCPI91_01301; CHECK-SD-NEXT: mov v0.d[1], v0.d[0]1302; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI91_0]1303; CHECK-SD-NEXT: tbl v0.8b, { v0.16b }, v1.8b1304; CHECK-SD-NEXT: ret1305;1306; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:1307; CHECK-GI: // %bb.0:1308; CHECK-GI-NEXT: movi v1.2d, #00000000000000001309; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01310; CHECK-GI-NEXT: adrp x8, .LCPI91_01311; CHECK-GI-NEXT: mov v1.d[1], v0.d[0]1312; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI91_0]1313; CHECK-GI-NEXT: tbl v0.16b, { v1.16b }, v0.16b1314; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q01315; CHECK-GI-NEXT: ret1316 %c = shufflevector <8 x i8> zeroinitializer, <8 x i8> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>1317 ret <8 x i8> %c1318}1319 1320; CHECK-SD-LABEL: .LCPI92_0:1321; CHECK-SD-NEXT: .byte 01322; CHECK-SD-NEXT: .byte 11323; CHECK-SD-NEXT: .byte 161324; CHECK-SD-NEXT: .byte 171325; CHECK-SD-NEXT: .byte 41326; CHECK-SD-NEXT: .byte 51327; CHECK-SD-NEXT: .byte 181328; CHECK-SD-NEXT: .byte 191329; CHECK-SD-NEXT: .byte 81330; CHECK-SD-NEXT: .byte 91331; CHECK-SD-NEXT: .byte 101332; CHECK-SD-NEXT: .byte 111333; CHECK-SD-NEXT: .byte 121334; CHECK-SD-NEXT: .byte 131335; CHECK-SD-NEXT: .byte 141336; CHECK-SD-NEXT: .byte 151337define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) {1338; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16:1339; CHECK-SD: // %bb.0:1340; CHECK-SD-NEXT: adrp x8, .LCPI92_01341; CHECK-SD-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q11342; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]1343; CHECK-SD-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q11344; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b1345; CHECK-SD-NEXT: ret1346;1347; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16:1348; CHECK-GI: // %bb.0:1349; CHECK-GI-NEXT: adrp x8, .LCPI92_01350; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q11351; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI92_0]1352; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q11353; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b1354; CHECK-GI-NEXT: ret1355 %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>1356 ret <8 x i16> %c1357}1358 1359; CHECK-SD-LABEL: .LCPI93_0:1360; CHECK-SD-NEXT: .hword 65535 // 0xffff1361; CHECK-SD-NEXT: .hword 0 // 0x01362; CHECK-SD-NEXT: .hword 65535 // 0xffff1363; CHECK-SD-NEXT: .hword 0 // 0x01364; CHECK-SD-NEXT: .hword 65535 // 0xffff1365; CHECK-SD-NEXT: .hword 65535 // 0xffff1366; CHECK-SD-NEXT: .hword 65535 // 0xffff1367; CHECK-SD-NEXT: .hword 65535 // 0xffff1368define <8 x i16> @vselect_equivalent_shuffle_v8i16_zero(<8 x i16> %a) {1369; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zero:1370; CHECK-SD: // %bb.0:1371; CHECK-SD-NEXT: adrp x8, .LCPI93_01372; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI93_0]1373; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b1374; CHECK-SD-NEXT: ret1375;1376; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zero:1377; CHECK-GI: // %bb.0:1378; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q0_q11379; CHECK-GI-NEXT: adrp x8, .LCPI93_01380; CHECK-GI-NEXT: movi v1.2d, #00000000000000001381; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI93_0]1382; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b1383; CHECK-GI-NEXT: ret1384 %c = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>1385 ret <8 x i16> %c1386}1387 1388; CHECK-SD: .byte 01389; CHECK-SD: .byte 11390; CHECK-SD: .byte 2551391; CHECK-SD: .byte 2551392; CHECK-SD: .byte 41393; CHECK-SD: .byte 51394; CHECK-SD: .byte 2551395; CHECK-SD: .byte 2551396; CHECK-SD: .byte 81397; CHECK-SD: .byte 91398; CHECK-SD: .byte 101399; CHECK-SD: .byte 111400; CHECK-SD: .byte 121401; CHECK-SD: .byte 131402; CHECK-SD: .byte 141403; CHECK-SD: .byte 151404define <8 x i16> @vselect_equivalent_shuffle_v8i16_zeroswap(<8 x i16> %a) {1405; CHECK-SD-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:1406; CHECK-SD: // %bb.0:1407; CHECK-SD-NEXT: adrp x8, .LCPI94_01408; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]1409; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b1410; CHECK-SD-NEXT: ret1411;1412; CHECK-GI-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:1413; CHECK-GI: // %bb.0:1414; CHECK-GI-NEXT: // kill: def $q0 killed $q0 def $q31_q01415; CHECK-GI-NEXT: adrp x8, .LCPI94_01416; CHECK-GI-NEXT: movi v31.2d, #00000000000000001417; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI94_0]1418; CHECK-GI-NEXT: tbl v0.16b, { v31.16b, v0.16b }, v1.16b1419; CHECK-GI-NEXT: ret1420 %c = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>1421 ret <8 x i16> %c1422}1423 1424define <4 x i16> @vselect_equivalent_shuffle_v4i16(<4 x i16> %a, <4 x i16> %b) {1425; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i16:1426; CHECK-SD: // %bb.0:1427; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01428; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11429; CHECK-SD-NEXT: mov v0.h[1], v1.h[0]1430; CHECK-SD-NEXT: mov v0.h[2], v1.h[1]1431; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q01432; CHECK-SD-NEXT: ret1433;1434; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i16:1435; CHECK-GI: // %bb.0:1436; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01437; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11438; CHECK-GI-NEXT: adrp x8, .LCPI95_01439; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]1440; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI95_0]1441; CHECK-GI-NEXT: tbl v0.16b, { v0.16b }, v1.16b1442; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q01443; CHECK-GI-NEXT: ret1444 %c = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>1445 ret <4 x i16> %c1446}1447 1448define <4 x i32> @vselect_equivalent_shuffle_v4i32(<4 x i32> %a, <4 x i32> %b) {1449; CHECK-SD-LABEL: vselect_equivalent_shuffle_v4i32:1450; CHECK-SD: // %bb.0:1451; CHECK-SD-NEXT: mov v0.s[1], v1.s[0]1452; CHECK-SD-NEXT: mov v0.s[2], v1.s[1]1453; CHECK-SD-NEXT: ret1454;1455; CHECK-GI-LABEL: vselect_equivalent_shuffle_v4i32:1456; CHECK-GI: // %bb.0:1457; CHECK-GI-NEXT: adrp x8, .LCPI96_01458; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q11459; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI96_0]1460; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q11461; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b1462; CHECK-GI-NEXT: ret1463 %c = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 5, i32 3>1464 ret <4 x i32> %c1465}1466 1467define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {1468; CHECK-SD-LABEL: vselect_cmp_ne:1469; CHECK-SD: // %bb.0:1470; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b1471; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b1472; CHECK-SD-NEXT: ret1473;1474; CHECK-GI-LABEL: vselect_cmp_ne:1475; CHECK-GI: // %bb.0:1476; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b1477; CHECK-GI-NEXT: mvn v0.8b, v0.8b1478; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b1479; CHECK-GI-NEXT: ret1480 %cmp = icmp ne <8 x i8> %a, %b1481 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c1482 ret <8 x i8> %d1483}1484 1485define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {1486; CHECK-LABEL: vselect_cmp_eq:1487; CHECK: // %bb.0:1488; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b1489; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b1490; CHECK-NEXT: ret1491 %cmp = icmp eq <8 x i8> %a, %b1492 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c1493 ret <8 x i8> %d1494}1495 1496define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {1497; CHECK-SD-LABEL: vselect_cmpz_ne:1498; CHECK-SD: // %bb.0:1499; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, #01500; CHECK-SD-NEXT: bsl v0.8b, v2.8b, v1.8b1501; CHECK-SD-NEXT: ret1502;1503; CHECK-GI-LABEL: vselect_cmpz_ne:1504; CHECK-GI: // %bb.0:1505; CHECK-GI-NEXT: cmtst v0.8b, v0.8b, v0.8b1506; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b1507; CHECK-GI-NEXT: ret1508 %cmp = icmp ne <8 x i8> %a, zeroinitializer1509 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c1510 ret <8 x i8> %d1511}1512 1513define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {1514; CHECK-LABEL: vselect_cmpz_eq:1515; CHECK: // %bb.0:1516; CHECK-NEXT: cmeq v0.8b, v0.8b, #01517; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b1518; CHECK-NEXT: ret1519 %cmp = icmp eq <8 x i8> %a, zeroinitializer1520 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c1521 ret <8 x i8> %d1522}1523 1524define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {1525; CHECK-LABEL: vselect_tst:1526; CHECK: // %bb.0:1527; CHECK-NEXT: and v0.8b, v0.8b, v1.8b1528; CHECK-NEXT: cmeq v0.8b, v0.8b, #01529; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b1530; CHECK-NEXT: ret1531 %tmp3 = and <8 x i8> %a, %b1532 %tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer1533 %d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b1534 ret <8 x i8> %d1535}1536 1537define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {1538; CHECK-LABEL: sext_tst:1539; CHECK: // %bb.0:1540; CHECK-NEXT: cmtst v0.8b, v0.8b, v1.8b1541; CHECK-NEXT: ret1542 %tmp3 = and <8 x i8> %a, %b1543 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer1544 %d = sext <8 x i1> %tmp4 to <8 x i8>1545 ret <8 x i8> %d1546}1547 1548define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {1549; CHECK-LABEL: bsl2xi64:1550; CHECK: // %bb.0:1551; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b1552; CHECK-NEXT: ret1553 %1 = and <2 x i64> %v1, %v21554 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>1555 %3 = and <2 x i64> %2, %v31556 %4 = or <2 x i64> %1, %31557 ret <2 x i64> %41558}1559 1560define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {1561; CHECK-SD-LABEL: orrimm8b_as_orrimm4h_lsl0:1562; CHECK-SD: // %bb.0:1563; CHECK-SD-NEXT: orr v0.4h, #2551564; CHECK-SD-NEXT: ret1565;1566; CHECK-GI-LABEL: orrimm8b_as_orrimm4h_lsl0:1567; CHECK-GI: // %bb.0:1568; CHECK-GI-NEXT: adrp x8, .LCPI104_01569; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI104_0]1570; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b1571; CHECK-GI-NEXT: ret1572 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>1573 ret <8 x i8> %val1574}1575 1576define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {1577; CHECK-SD-LABEL: orrimm8b_as_orimm4h_lsl8:1578; CHECK-SD: // %bb.0:1579; CHECK-SD-NEXT: orr v0.4h, #255, lsl #81580; CHECK-SD-NEXT: ret1581;1582; CHECK-GI-LABEL: orrimm8b_as_orimm4h_lsl8:1583; CHECK-GI: // %bb.0:1584; CHECK-GI-NEXT: adrp x8, .LCPI105_01585; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI105_0]1586; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b1587; CHECK-GI-NEXT: ret1588 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>1589 ret <8 x i8> %val1590}1591 1592define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {1593; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl0:1594; CHECK-SD: // %bb.0:1595; CHECK-SD-NEXT: orr v0.8h, #2551596; CHECK-SD-NEXT: ret1597;1598; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl0:1599; CHECK-GI: // %bb.0:1600; CHECK-GI-NEXT: adrp x8, .LCPI106_01601; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI106_0]1602; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b1603; CHECK-GI-NEXT: ret1604 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>1605 ret <16 x i8> %val1606}1607 1608define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {1609; CHECK-SD-LABEL: orimm16b_as_orrimm8h_lsl8:1610; CHECK-SD: // %bb.0:1611; CHECK-SD-NEXT: orr v0.8h, #255, lsl #81612; CHECK-SD-NEXT: ret1613;1614; CHECK-GI-LABEL: orimm16b_as_orrimm8h_lsl8:1615; CHECK-GI: // %bb.0:1616; CHECK-GI-NEXT: adrp x8, .LCPI107_01617; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI107_0]1618; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b1619; CHECK-GI-NEXT: ret1620 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>1621 ret <16 x i8> %val1622}1623 1624define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {1625; CHECK-SD-LABEL: and8imm2s_lsl0:1626; CHECK-SD: // %bb.0:1627; CHECK-SD-NEXT: bic v0.2s, #2551628; CHECK-SD-NEXT: ret1629;1630; CHECK-GI-LABEL: and8imm2s_lsl0:1631; CHECK-GI: // %bb.0:1632; CHECK-GI-NEXT: adrp x8, .LCPI108_01633; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI108_0]1634; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1635; CHECK-GI-NEXT: ret1636 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>1637 ret <8 x i8> %tmp11638}1639 1640define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {1641; CHECK-SD-LABEL: and8imm2s_lsl8:1642; CHECK-SD: // %bb.0:1643; CHECK-SD-NEXT: bic v0.2s, #255, lsl #81644; CHECK-SD-NEXT: ret1645;1646; CHECK-GI-LABEL: and8imm2s_lsl8:1647; CHECK-GI: // %bb.0:1648; CHECK-GI-NEXT: adrp x8, .LCPI109_01649; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI109_0]1650; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1651; CHECK-GI-NEXT: ret1652 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>1653 ret <8 x i8> %tmp11654}1655 1656define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {1657; CHECK-SD-LABEL: and8imm2s_lsl16:1658; CHECK-SD: // %bb.0:1659; CHECK-SD-NEXT: bic v0.2s, #255, lsl #161660; CHECK-SD-NEXT: ret1661;1662; CHECK-GI-LABEL: and8imm2s_lsl16:1663; CHECK-GI: // %bb.0:1664; CHECK-GI-NEXT: adrp x8, .LCPI110_01665; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI110_0]1666; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1667; CHECK-GI-NEXT: ret1668 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>1669 ret <8 x i8> %tmp11670}1671 1672define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {1673; CHECK-SD-LABEL: and8imm2s_lsl24:1674; CHECK-SD: // %bb.0:1675; CHECK-SD-NEXT: bic v0.2s, #254, lsl #241676; CHECK-SD-NEXT: ret1677;1678; CHECK-GI-LABEL: and8imm2s_lsl24:1679; CHECK-GI: // %bb.0:1680; CHECK-GI-NEXT: adrp x8, .LCPI111_01681; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI111_0]1682; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1683; CHECK-GI-NEXT: ret1684 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>1685 ret <8 x i8> %tmp11686}1687 1688define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {1689; CHECK-SD-LABEL: and16imm2s_lsl0:1690; CHECK-SD: // %bb.0:1691; CHECK-SD-NEXT: bic v0.2s, #2551692; CHECK-SD-NEXT: ret1693;1694; CHECK-GI-LABEL: and16imm2s_lsl0:1695; CHECK-GI: // %bb.0:1696; CHECK-GI-NEXT: adrp x8, .LCPI112_01697; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI112_0]1698; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1699; CHECK-GI-NEXT: ret1700 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>1701 ret <4 x i16> %tmp11702}1703 1704define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {1705; CHECK-SD-LABEL: and16imm2s_lsl8:1706; CHECK-SD: // %bb.0:1707; CHECK-SD-NEXT: bic v0.2s, #255, lsl #81708; CHECK-SD-NEXT: ret1709;1710; CHECK-GI-LABEL: and16imm2s_lsl8:1711; CHECK-GI: // %bb.0:1712; CHECK-GI-NEXT: adrp x8, .LCPI113_01713; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI113_0]1714; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1715; CHECK-GI-NEXT: ret1716 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>1717 ret <4 x i16> %tmp11718}1719 1720define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {1721; CHECK-SD-LABEL: and16imm2s_lsl16:1722; CHECK-SD: // %bb.0:1723; CHECK-SD-NEXT: bic v0.2s, #255, lsl #161724; CHECK-SD-NEXT: ret1725;1726; CHECK-GI-LABEL: and16imm2s_lsl16:1727; CHECK-GI: // %bb.0:1728; CHECK-GI-NEXT: adrp x8, .LCPI114_01729; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI114_0]1730; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1731; CHECK-GI-NEXT: ret1732 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>1733 ret <4 x i16> %tmp11734}1735 1736define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {1737; CHECK-SD-LABEL: and16imm2s_lsl24:1738; CHECK-SD: // %bb.0:1739; CHECK-SD-NEXT: bic v0.2s, #254, lsl #241740; CHECK-SD-NEXT: ret1741;1742; CHECK-GI-LABEL: and16imm2s_lsl24:1743; CHECK-GI: // %bb.0:1744; CHECK-GI-NEXT: adrp x8, .LCPI115_01745; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI115_0]1746; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b1747; CHECK-GI-NEXT: ret1748 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>1749 ret <4 x i16> %tmp11750}1751 1752 1753define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {1754; CHECK-SD-LABEL: and64imm2s_lsl0:1755; CHECK-SD: // %bb.0:1756; CHECK-SD-NEXT: bic v0.2s, #2551757; CHECK-SD-NEXT: ret1758;1759; CHECK-GI-LABEL: and64imm2s_lsl0:1760; CHECK-GI: // %bb.0:1761; CHECK-GI-NEXT: fmov x8, d01762; CHECK-GI-NEXT: and x8, x8, #0xffffff00ffffff001763; CHECK-GI-NEXT: fmov d0, x81764; CHECK-GI-NEXT: ret1765 %tmp1 = and <1 x i64> %a, < i64 -1095216660736>1766 ret <1 x i64> %tmp11767}1768 1769define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {1770; CHECK-SD-LABEL: and64imm2s_lsl8:1771; CHECK-SD: // %bb.0:1772; CHECK-SD-NEXT: bic v0.2s, #255, lsl #81773; CHECK-SD-NEXT: ret1774;1775; CHECK-GI-LABEL: and64imm2s_lsl8:1776; CHECK-GI: // %bb.0:1777; CHECK-GI-NEXT: fmov x8, d01778; CHECK-GI-NEXT: and x8, x8, #0xffff00ffffff00ff1779; CHECK-GI-NEXT: fmov d0, x81780; CHECK-GI-NEXT: ret1781 %tmp1 = and <1 x i64> %a, < i64 -280375465148161>1782 ret <1 x i64> %tmp11783}1784 1785define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {1786; CHECK-SD-LABEL: and64imm2s_lsl16:1787; CHECK-SD: // %bb.0:1788; CHECK-SD-NEXT: bic v0.2s, #255, lsl #161789; CHECK-SD-NEXT: ret1790;1791; CHECK-GI-LABEL: and64imm2s_lsl16:1792; CHECK-GI: // %bb.0:1793; CHECK-GI-NEXT: fmov x8, d01794; CHECK-GI-NEXT: and x8, x8, #0xff00ffffff00ffff1795; CHECK-GI-NEXT: fmov d0, x81796; CHECK-GI-NEXT: ret1797 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961>1798 ret <1 x i64> %tmp11799}1800 1801define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {1802; CHECK-SD-LABEL: and64imm2s_lsl24:1803; CHECK-SD: // %bb.0:1804; CHECK-SD-NEXT: bic v0.2s, #254, lsl #241805; CHECK-SD-NEXT: ret1806;1807; CHECK-GI-LABEL: and64imm2s_lsl24:1808; CHECK-GI: // %bb.0:1809; CHECK-GI-NEXT: fmov x8, d01810; CHECK-GI-NEXT: and x8, x8, #0x1ffffff01ffffff1811; CHECK-GI-NEXT: fmov d0, x81812; CHECK-GI-NEXT: ret1813 %tmp1 = and <1 x i64> %a, < i64 144115183814443007>1814 ret <1 x i64> %tmp11815}1816 1817define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {1818; CHECK-SD-LABEL: and8imm4s_lsl0:1819; CHECK-SD: // %bb.0:1820; CHECK-SD-NEXT: bic v0.4s, #2551821; CHECK-SD-NEXT: ret1822;1823; CHECK-GI-LABEL: and8imm4s_lsl0:1824; CHECK-GI: // %bb.0:1825; CHECK-GI-NEXT: adrp x8, .LCPI120_01826; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI120_0]1827; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1828; CHECK-GI-NEXT: ret1829 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>1830 ret <16 x i8> %tmp11831}1832 1833define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {1834; CHECK-SD-LABEL: and8imm4s_lsl8:1835; CHECK-SD: // %bb.0:1836; CHECK-SD-NEXT: bic v0.4s, #255, lsl #81837; CHECK-SD-NEXT: ret1838;1839; CHECK-GI-LABEL: and8imm4s_lsl8:1840; CHECK-GI: // %bb.0:1841; CHECK-GI-NEXT: adrp x8, .LCPI121_01842; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI121_0]1843; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1844; CHECK-GI-NEXT: ret1845 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>1846 ret <16 x i8> %tmp11847}1848 1849define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {1850; CHECK-SD-LABEL: and8imm4s_lsl16:1851; CHECK-SD: // %bb.0:1852; CHECK-SD-NEXT: bic v0.4s, #255, lsl #161853; CHECK-SD-NEXT: ret1854;1855; CHECK-GI-LABEL: and8imm4s_lsl16:1856; CHECK-GI: // %bb.0:1857; CHECK-GI-NEXT: adrp x8, .LCPI122_01858; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI122_0]1859; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1860; CHECK-GI-NEXT: ret1861 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>1862 ret <16 x i8> %tmp11863}1864 1865define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {1866; CHECK-SD-LABEL: and8imm4s_lsl24:1867; CHECK-SD: // %bb.0:1868; CHECK-SD-NEXT: bic v0.4s, #254, lsl #241869; CHECK-SD-NEXT: ret1870;1871; CHECK-GI-LABEL: and8imm4s_lsl24:1872; CHECK-GI: // %bb.0:1873; CHECK-GI-NEXT: adrp x8, .LCPI123_01874; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI123_0]1875; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1876; CHECK-GI-NEXT: ret1877 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>1878 ret <16 x i8> %tmp11879}1880 1881define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {1882; CHECK-SD-LABEL: and16imm4s_lsl0:1883; CHECK-SD: // %bb.0:1884; CHECK-SD-NEXT: bic v0.4s, #2551885; CHECK-SD-NEXT: ret1886;1887; CHECK-GI-LABEL: and16imm4s_lsl0:1888; CHECK-GI: // %bb.0:1889; CHECK-GI-NEXT: adrp x8, .LCPI124_01890; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI124_0]1891; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1892; CHECK-GI-NEXT: ret1893 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>1894 ret <8 x i16> %tmp11895}1896 1897define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {1898; CHECK-SD-LABEL: and16imm4s_lsl8:1899; CHECK-SD: // %bb.0:1900; CHECK-SD-NEXT: bic v0.4s, #255, lsl #81901; CHECK-SD-NEXT: ret1902;1903; CHECK-GI-LABEL: and16imm4s_lsl8:1904; CHECK-GI: // %bb.0:1905; CHECK-GI-NEXT: adrp x8, .LCPI125_01906; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI125_0]1907; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1908; CHECK-GI-NEXT: ret1909 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>1910 ret <8 x i16> %tmp11911}1912 1913define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {1914; CHECK-SD-LABEL: and16imm4s_lsl16:1915; CHECK-SD: // %bb.0:1916; CHECK-SD-NEXT: bic v0.4s, #255, lsl #161917; CHECK-SD-NEXT: ret1918;1919; CHECK-GI-LABEL: and16imm4s_lsl16:1920; CHECK-GI: // %bb.0:1921; CHECK-GI-NEXT: adrp x8, .LCPI126_01922; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI126_0]1923; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1924; CHECK-GI-NEXT: ret1925 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>1926 ret <8 x i16> %tmp11927}1928 1929define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {1930; CHECK-SD-LABEL: and16imm4s_lsl24:1931; CHECK-SD: // %bb.0:1932; CHECK-SD-NEXT: bic v0.4s, #254, lsl #241933; CHECK-SD-NEXT: ret1934;1935; CHECK-GI-LABEL: and16imm4s_lsl24:1936; CHECK-GI: // %bb.0:1937; CHECK-GI-NEXT: adrp x8, .LCPI127_01938; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI127_0]1939; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1940; CHECK-GI-NEXT: ret1941 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>1942 ret <8 x i16> %tmp11943}1944 1945define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {1946; CHECK-SD-LABEL: and64imm4s_lsl0:1947; CHECK-SD: // %bb.0:1948; CHECK-SD-NEXT: bic v0.4s, #2551949; CHECK-SD-NEXT: ret1950;1951; CHECK-GI-LABEL: and64imm4s_lsl0:1952; CHECK-GI: // %bb.0:1953; CHECK-GI-NEXT: movi v1.2d, #0xffffff00ffffff001954; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1955; CHECK-GI-NEXT: ret1956 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>1957 ret <2 x i64> %tmp11958}1959 1960define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {1961; CHECK-SD-LABEL: and64imm4s_lsl8:1962; CHECK-SD: // %bb.0:1963; CHECK-SD-NEXT: bic v0.4s, #255, lsl #81964; CHECK-SD-NEXT: ret1965;1966; CHECK-GI-LABEL: and64imm4s_lsl8:1967; CHECK-GI: // %bb.0:1968; CHECK-GI-NEXT: movi v1.2d, #0xffff00ffffff00ff1969; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1970; CHECK-GI-NEXT: ret1971 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>1972 ret <2 x i64> %tmp11973}1974 1975define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {1976; CHECK-SD-LABEL: and64imm4s_lsl16:1977; CHECK-SD: // %bb.0:1978; CHECK-SD-NEXT: bic v0.4s, #255, lsl #161979; CHECK-SD-NEXT: ret1980;1981; CHECK-GI-LABEL: and64imm4s_lsl16:1982; CHECK-GI: // %bb.0:1983; CHECK-GI-NEXT: movi v1.2d, #0xff00ffffff00ffff1984; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b1985; CHECK-GI-NEXT: ret1986 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>1987 ret <2 x i64> %tmp11988}1989 1990define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {1991; CHECK-SD-LABEL: and64imm4s_lsl24:1992; CHECK-SD: // %bb.0:1993; CHECK-SD-NEXT: bic v0.4s, #254, lsl #241994; CHECK-SD-NEXT: ret1995;1996; CHECK-GI-LABEL: and64imm4s_lsl24:1997; CHECK-GI: // %bb.0:1998; CHECK-GI-NEXT: mvni v1.4s, #254, lsl #241999; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b2000; CHECK-GI-NEXT: ret2001 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>2002 ret <2 x i64> %tmp12003}2004 2005define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {2006; CHECK-SD-LABEL: and8imm4h_lsl0:2007; CHECK-SD: // %bb.0:2008; CHECK-SD-NEXT: bic v0.4h, #2552009; CHECK-SD-NEXT: ret2010;2011; CHECK-GI-LABEL: and8imm4h_lsl0:2012; CHECK-GI: // %bb.0:2013; CHECK-GI-NEXT: adrp x8, .LCPI132_02014; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI132_0]2015; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b2016; CHECK-GI-NEXT: ret2017 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>2018 ret <8 x i8> %tmp12019}2020 2021define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {2022; CHECK-SD-LABEL: and8imm4h_lsl8:2023; CHECK-SD: // %bb.0:2024; CHECK-SD-NEXT: bic v0.4h, #255, lsl #82025; CHECK-SD-NEXT: ret2026;2027; CHECK-GI-LABEL: and8imm4h_lsl8:2028; CHECK-GI: // %bb.0:2029; CHECK-GI-NEXT: adrp x8, .LCPI133_02030; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI133_0]2031; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b2032; CHECK-GI-NEXT: ret2033 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>2034 ret <8 x i8> %tmp12035}2036 2037define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {2038; CHECK-SD-LABEL: and16imm4h_lsl0:2039; CHECK-SD: // %bb.0:2040; CHECK-SD-NEXT: bic v0.4h, #2552041; CHECK-SD-NEXT: ret2042;2043; CHECK-GI-LABEL: and16imm4h_lsl0:2044; CHECK-GI: // %bb.0:2045; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff002046; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b2047; CHECK-GI-NEXT: ret2048 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>2049 ret <2 x i32> %tmp12050}2051 2052define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {2053; CHECK-SD-LABEL: and16imm4h_lsl8:2054; CHECK-SD: // %bb.0:2055; CHECK-SD-NEXT: bic v0.4h, #255, lsl #82056; CHECK-SD-NEXT: ret2057;2058; CHECK-GI-LABEL: and16imm4h_lsl8:2059; CHECK-GI: // %bb.0:2060; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff2061; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b2062; CHECK-GI-NEXT: ret2063 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>2064 ret <2 x i32> %tmp12065}2066 2067define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {2068; CHECK-SD-LABEL: and64imm4h_lsl0:2069; CHECK-SD: // %bb.0:2070; CHECK-SD-NEXT: bic v0.4h, #2552071; CHECK-SD-NEXT: ret2072;2073; CHECK-GI-LABEL: and64imm4h_lsl0:2074; CHECK-GI: // %bb.0:2075; CHECK-GI-NEXT: fmov x8, d02076; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff002077; CHECK-GI-NEXT: fmov d0, x82078; CHECK-GI-NEXT: ret2079 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696>2080 ret <1 x i64> %tmp12081}2082 2083define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {2084; CHECK-SD-LABEL: and64imm4h_lsl8:2085; CHECK-SD: // %bb.0:2086; CHECK-SD-NEXT: bic v0.4h, #255, lsl #82087; CHECK-SD-NEXT: ret2088;2089; CHECK-GI-LABEL: and64imm4h_lsl8:2090; CHECK-GI: // %bb.0:2091; CHECK-GI-NEXT: fmov x8, d02092; CHECK-GI-NEXT: and x8, x8, #0xff00ff00ff00ff2093; CHECK-GI-NEXT: fmov d0, x82094; CHECK-GI-NEXT: ret2095 %tmp1 = and <1 x i64> %a, < i64 71777214294589695>2096 ret <1 x i64> %tmp12097}2098 2099define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {2100; CHECK-SD-LABEL: and8imm8h_lsl0:2101; CHECK-SD: // %bb.0:2102; CHECK-SD-NEXT: bic v0.8h, #2552103; CHECK-SD-NEXT: ret2104;2105; CHECK-GI-LABEL: and8imm8h_lsl0:2106; CHECK-GI: // %bb.0:2107; CHECK-GI-NEXT: adrp x8, .LCPI138_02108; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI138_0]2109; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b2110; CHECK-GI-NEXT: ret2111 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >2112 ret <16 x i8> %tmp12113}2114 2115define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {2116; CHECK-SD-LABEL: and8imm8h_lsl8:2117; CHECK-SD: // %bb.0:2118; CHECK-SD-NEXT: bic v0.8h, #255, lsl #82119; CHECK-SD-NEXT: ret2120;2121; CHECK-GI-LABEL: and8imm8h_lsl8:2122; CHECK-GI: // %bb.0:2123; CHECK-GI-NEXT: adrp x8, .LCPI139_02124; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI139_0]2125; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b2126; CHECK-GI-NEXT: ret2127 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >2128 ret <16 x i8> %tmp12129}2130 2131define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {2132; CHECK-SD-LABEL: and16imm8h_lsl0:2133; CHECK-SD: // %bb.0:2134; CHECK-SD-NEXT: bic v0.8h, #2552135; CHECK-SD-NEXT: ret2136;2137; CHECK-GI-LABEL: and16imm8h_lsl0:2138; CHECK-GI: // %bb.0:2139; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff002140; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b2141; CHECK-GI-NEXT: ret2142 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>2143 ret <4 x i32> %tmp12144}2145 2146define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {2147; CHECK-SD-LABEL: and16imm8h_lsl8:2148; CHECK-SD: // %bb.0:2149; CHECK-SD-NEXT: bic v0.8h, #255, lsl #82150; CHECK-SD-NEXT: ret2151;2152; CHECK-GI-LABEL: and16imm8h_lsl8:2153; CHECK-GI: // %bb.0:2154; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff2155; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b2156; CHECK-GI-NEXT: ret2157 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>2158 ret <4 x i32> %tmp12159}2160 2161define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {2162; CHECK-SD-LABEL: and64imm8h_lsl0:2163; CHECK-SD: // %bb.0:2164; CHECK-SD-NEXT: bic v0.8h, #2552165; CHECK-SD-NEXT: ret2166;2167; CHECK-GI-LABEL: and64imm8h_lsl0:2168; CHECK-GI: // %bb.0:2169; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff002170; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b2171; CHECK-GI-NEXT: ret2172 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>2173 ret <2 x i64> %tmp12174}2175 2176define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {2177; CHECK-SD-LABEL: and64imm8h_lsl8:2178; CHECK-SD: // %bb.0:2179; CHECK-SD-NEXT: bic v0.8h, #255, lsl #82180; CHECK-SD-NEXT: ret2181;2182; CHECK-GI-LABEL: and64imm8h_lsl8:2183; CHECK-GI: // %bb.0:2184; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff2185; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b2186; CHECK-GI-NEXT: ret2187 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>2188 ret <2 x i64> %tmp12189}2190 2191define <8 x i16> @bic_shifted_knownbits(<8 x i16> %v) {2192; CHECK-SD-LABEL: bic_shifted_knownbits:2193; CHECK-SD: // %bb.0: // %entry2194; CHECK-SD-NEXT: ushr v0.8h, v0.8h, #92195; CHECK-SD-NEXT: bic v0.8h, #1262196; CHECK-SD-NEXT: ret2197;2198; CHECK-GI-LABEL: bic_shifted_knownbits:2199; CHECK-GI: // %bb.0: // %entry2200; CHECK-GI-NEXT: movi v1.8h, #12201; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #92202; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b2203; CHECK-GI-NEXT: ret2204entry:2205 %vshr_n = lshr <8 x i16> %v, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>2206 %and.i = and <8 x i16> %vshr_n, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>2207 ret <8 x i16> %and.i2208}2209 2210define <8 x i32> @bic_shifted_knownbits2(<8 x i16> %v) {2211; CHECK-SD-LABEL: bic_shifted_knownbits2:2212; CHECK-SD: // %bb.0: // %entry2213; CHECK-SD-NEXT: ushll v2.4s, v0.4h, #02214; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #02215; CHECK-SD-NEXT: bic v2.4s, #255, lsl #82216; CHECK-SD-NEXT: bic v1.4s, #255, lsl #82217; CHECK-SD-NEXT: mov v0.16b, v2.16b2218; CHECK-SD-NEXT: ret2219;2220; CHECK-GI-LABEL: bic_shifted_knownbits2:2221; CHECK-GI: // %bb.0: // %entry2222; CHECK-GI-NEXT: adrp x8, .LCPI145_02223; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #02224; CHECK-GI-NEXT: ushll2 v2.4s, v0.8h, #02225; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI145_0]2226; CHECK-GI-NEXT: and v0.16b, v1.16b, v3.16b2227; CHECK-GI-NEXT: and v1.16b, v2.16b, v3.16b2228; CHECK-GI-NEXT: ret2229entry:2230 %vshr_n = zext <8 x i16> %v to <8 x i32>2231 %and.i = and <8 x i32> %vshr_n, <i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975, i32 4293918975>2232 ret <8 x i32> %and.i2233}2234 2235define <8 x i32> @bic_shifted_knownbits3(<8 x i16> %v) {2236; CHECK-SD-LABEL: bic_shifted_knownbits3:2237; CHECK-SD: // %bb.0:2238; CHECK-SD-NEXT: bic v0.8h, #255, lsl #82239; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #02240; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #02241; CHECK-SD-NEXT: ret2242;2243; CHECK-GI-LABEL: bic_shifted_knownbits3:2244; CHECK-GI: // %bb.0:2245; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff2246; CHECK-GI-NEXT: and v1.16b, v0.16b, v1.16b2247; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #02248; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #02249; CHECK-GI-NEXT: ret2250 %a = and <8 x i16> %v, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>2251 %and.i = zext <8 x i16> %a to <8 x i32>2252 ret <8 x i32> %and.i2253}2254 2255 2256define <8 x i32> @bic_shifted_knownbits4(<8 x i32> %v) {2257; CHECK-SD-LABEL: bic_shifted_knownbits4:2258; CHECK-SD: // %bb.0: // %entry2259; CHECK-SD-NEXT: shl v1.4s, v1.4s, #82260; CHECK-SD-NEXT: shl v0.4s, v0.4s, #82261; CHECK-SD-NEXT: bic v0.4s, #255, lsl #82262; CHECK-SD-NEXT: bic v1.4s, #255, lsl #82263; CHECK-SD-NEXT: ret2264;2265; CHECK-GI-LABEL: bic_shifted_knownbits4:2266; CHECK-GI: // %bb.0: // %entry2267; CHECK-GI-NEXT: movi v2.2d, #0xffff0000ffff00002268; CHECK-GI-NEXT: shl v0.4s, v0.4s, #82269; CHECK-GI-NEXT: shl v1.4s, v1.4s, #82270; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b2271; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b2272; CHECK-GI-NEXT: ret2273entry:2274 %vshr_n = shl <8 x i32> %v, <i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>2275 %and.i = and <8 x i32> %vshr_n, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>2276 ret <8 x i32> %and.i2277}2278 2279define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {2280; CHECK-SD-LABEL: orr8imm2s_lsl0:2281; CHECK-SD: // %bb.0:2282; CHECK-SD-NEXT: orr v0.2s, #2552283; CHECK-SD-NEXT: ret2284;2285; CHECK-GI-LABEL: orr8imm2s_lsl0:2286; CHECK-GI: // %bb.0:2287; CHECK-GI-NEXT: adrp x8, .LCPI148_02288; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI148_0]2289; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2290; CHECK-GI-NEXT: ret2291 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>2292 ret <8 x i8> %tmp12293}2294 2295define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {2296; CHECK-SD-LABEL: orr8imm2s_lsl8:2297; CHECK-SD: // %bb.0:2298; CHECK-SD-NEXT: orr v0.2s, #255, lsl #82299; CHECK-SD-NEXT: ret2300;2301; CHECK-GI-LABEL: orr8imm2s_lsl8:2302; CHECK-GI: // %bb.0:2303; CHECK-GI-NEXT: adrp x8, .LCPI149_02304; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI149_0]2305; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2306; CHECK-GI-NEXT: ret2307 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>2308 ret <8 x i8> %tmp12309}2310 2311define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {2312; CHECK-SD-LABEL: orr8imm2s_lsl16:2313; CHECK-SD: // %bb.0:2314; CHECK-SD-NEXT: orr v0.2s, #255, lsl #162315; CHECK-SD-NEXT: ret2316;2317; CHECK-GI-LABEL: orr8imm2s_lsl16:2318; CHECK-GI: // %bb.0:2319; CHECK-GI-NEXT: adrp x8, .LCPI150_02320; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI150_0]2321; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2322; CHECK-GI-NEXT: ret2323 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>2324 ret <8 x i8> %tmp12325}2326 2327define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {2328; CHECK-SD-LABEL: orr8imm2s_lsl24:2329; CHECK-SD: // %bb.0:2330; CHECK-SD-NEXT: orr v0.2s, #255, lsl #242331; CHECK-SD-NEXT: ret2332;2333; CHECK-GI-LABEL: orr8imm2s_lsl24:2334; CHECK-GI: // %bb.0:2335; CHECK-GI-NEXT: adrp x8, .LCPI151_02336; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI151_0]2337; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2338; CHECK-GI-NEXT: ret2339 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>2340 ret <8 x i8> %tmp12341}2342 2343define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {2344; CHECK-SD-LABEL: orr16imm2s_lsl0:2345; CHECK-SD: // %bb.0:2346; CHECK-SD-NEXT: orr v0.2s, #2552347; CHECK-SD-NEXT: ret2348;2349; CHECK-GI-LABEL: orr16imm2s_lsl0:2350; CHECK-GI: // %bb.0:2351; CHECK-GI-NEXT: adrp x8, .LCPI152_02352; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI152_0]2353; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2354; CHECK-GI-NEXT: ret2355 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>2356 ret <4 x i16> %tmp12357}2358 2359define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {2360; CHECK-SD-LABEL: orr16imm2s_lsl8:2361; CHECK-SD: // %bb.0:2362; CHECK-SD-NEXT: orr v0.2s, #255, lsl #82363; CHECK-SD-NEXT: ret2364;2365; CHECK-GI-LABEL: orr16imm2s_lsl8:2366; CHECK-GI: // %bb.0:2367; CHECK-GI-NEXT: adrp x8, .LCPI153_02368; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI153_0]2369; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2370; CHECK-GI-NEXT: ret2371 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>2372 ret <4 x i16> %tmp12373}2374 2375define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {2376; CHECK-SD-LABEL: orr16imm2s_lsl16:2377; CHECK-SD: // %bb.0:2378; CHECK-SD-NEXT: orr v0.2s, #255, lsl #162379; CHECK-SD-NEXT: ret2380;2381; CHECK-GI-LABEL: orr16imm2s_lsl16:2382; CHECK-GI: // %bb.0:2383; CHECK-GI-NEXT: adrp x8, .LCPI154_02384; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI154_0]2385; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2386; CHECK-GI-NEXT: ret2387 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>2388 ret <4 x i16> %tmp12389}2390 2391define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {2392; CHECK-SD-LABEL: orr16imm2s_lsl24:2393; CHECK-SD: // %bb.0:2394; CHECK-SD-NEXT: orr v0.2s, #255, lsl #242395; CHECK-SD-NEXT: ret2396;2397; CHECK-GI-LABEL: orr16imm2s_lsl24:2398; CHECK-GI: // %bb.0:2399; CHECK-GI-NEXT: adrp x8, .LCPI155_02400; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI155_0]2401; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2402; CHECK-GI-NEXT: ret2403 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>2404 ret <4 x i16> %tmp12405}2406 2407define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {2408; CHECK-SD-LABEL: orr64imm2s_lsl0:2409; CHECK-SD: // %bb.0:2410; CHECK-SD-NEXT: orr v0.2s, #2552411; CHECK-SD-NEXT: ret2412;2413; CHECK-GI-LABEL: orr64imm2s_lsl0:2414; CHECK-GI: // %bb.0:2415; CHECK-GI-NEXT: fmov x8, d02416; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff2417; CHECK-GI-NEXT: fmov d0, x82418; CHECK-GI-NEXT: ret2419 %tmp1 = or <1 x i64> %a, < i64 1095216660735>2420 ret <1 x i64> %tmp12421}2422 2423define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {2424; CHECK-SD-LABEL: orr64imm2s_lsl8:2425; CHECK-SD: // %bb.0:2426; CHECK-SD-NEXT: orr v0.2s, #255, lsl #82427; CHECK-SD-NEXT: ret2428;2429; CHECK-GI-LABEL: orr64imm2s_lsl8:2430; CHECK-GI: // %bb.0:2431; CHECK-GI-NEXT: fmov x8, d02432; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff002433; CHECK-GI-NEXT: fmov d0, x82434; CHECK-GI-NEXT: ret2435 %tmp1 = or <1 x i64> %a, < i64 280375465148160>2436 ret <1 x i64> %tmp12437}2438 2439define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {2440; CHECK-SD-LABEL: orr64imm2s_lsl16:2441; CHECK-SD: // %bb.0:2442; CHECK-SD-NEXT: orr v0.2s, #255, lsl #162443; CHECK-SD-NEXT: ret2444;2445; CHECK-GI-LABEL: orr64imm2s_lsl16:2446; CHECK-GI: // %bb.0:2447; CHECK-GI-NEXT: fmov x8, d02448; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff00002449; CHECK-GI-NEXT: fmov d0, x82450; CHECK-GI-NEXT: ret2451 %tmp1 = or <1 x i64> %a, < i64 71776119077928960>2452 ret <1 x i64> %tmp12453}2454 2455define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {2456; CHECK-SD-LABEL: orr64imm2s_lsl24:2457; CHECK-SD: // %bb.0:2458; CHECK-SD-NEXT: orr v0.2s, #255, lsl #242459; CHECK-SD-NEXT: ret2460;2461; CHECK-GI-LABEL: orr64imm2s_lsl24:2462; CHECK-GI: // %bb.0:2463; CHECK-GI-NEXT: fmov x8, d02464; CHECK-GI-NEXT: orr x8, x8, #0xff000000ff0000002465; CHECK-GI-NEXT: fmov d0, x82466; CHECK-GI-NEXT: ret2467 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856>2468 ret <1 x i64> %tmp12469}2470 2471define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {2472; CHECK-SD-LABEL: orr8imm4s_lsl0:2473; CHECK-SD: // %bb.0:2474; CHECK-SD-NEXT: orr v0.4s, #2552475; CHECK-SD-NEXT: ret2476;2477; CHECK-GI-LABEL: orr8imm4s_lsl0:2478; CHECK-GI: // %bb.0:2479; CHECK-GI-NEXT: adrp x8, .LCPI160_02480; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI160_0]2481; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2482; CHECK-GI-NEXT: ret2483 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>2484 ret <16 x i8> %tmp12485}2486 2487define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {2488; CHECK-SD-LABEL: orr8imm4s_lsl8:2489; CHECK-SD: // %bb.0:2490; CHECK-SD-NEXT: orr v0.4s, #255, lsl #82491; CHECK-SD-NEXT: ret2492;2493; CHECK-GI-LABEL: orr8imm4s_lsl8:2494; CHECK-GI: // %bb.0:2495; CHECK-GI-NEXT: adrp x8, .LCPI161_02496; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI161_0]2497; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2498; CHECK-GI-NEXT: ret2499 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>2500 ret <16 x i8> %tmp12501}2502 2503define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {2504; CHECK-SD-LABEL: orr8imm4s_lsl16:2505; CHECK-SD: // %bb.0:2506; CHECK-SD-NEXT: orr v0.4s, #255, lsl #162507; CHECK-SD-NEXT: ret2508;2509; CHECK-GI-LABEL: orr8imm4s_lsl16:2510; CHECK-GI: // %bb.0:2511; CHECK-GI-NEXT: adrp x8, .LCPI162_02512; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI162_0]2513; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2514; CHECK-GI-NEXT: ret2515 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>2516 ret <16 x i8> %tmp12517}2518 2519define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {2520; CHECK-SD-LABEL: orr8imm4s_lsl24:2521; CHECK-SD: // %bb.0:2522; CHECK-SD-NEXT: orr v0.4s, #255, lsl #242523; CHECK-SD-NEXT: ret2524;2525; CHECK-GI-LABEL: orr8imm4s_lsl24:2526; CHECK-GI: // %bb.0:2527; CHECK-GI-NEXT: adrp x8, .LCPI163_02528; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI163_0]2529; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2530; CHECK-GI-NEXT: ret2531 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>2532 ret <16 x i8> %tmp12533}2534 2535define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {2536; CHECK-SD-LABEL: orr16imm4s_lsl0:2537; CHECK-SD: // %bb.0:2538; CHECK-SD-NEXT: orr v0.4s, #2552539; CHECK-SD-NEXT: ret2540;2541; CHECK-GI-LABEL: orr16imm4s_lsl0:2542; CHECK-GI: // %bb.0:2543; CHECK-GI-NEXT: adrp x8, .LCPI164_02544; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI164_0]2545; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2546; CHECK-GI-NEXT: ret2547 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>2548 ret <8 x i16> %tmp12549}2550 2551define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {2552; CHECK-SD-LABEL: orr16imm4s_lsl8:2553; CHECK-SD: // %bb.0:2554; CHECK-SD-NEXT: orr v0.4s, #255, lsl #82555; CHECK-SD-NEXT: ret2556;2557; CHECK-GI-LABEL: orr16imm4s_lsl8:2558; CHECK-GI: // %bb.0:2559; CHECK-GI-NEXT: adrp x8, .LCPI165_02560; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI165_0]2561; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2562; CHECK-GI-NEXT: ret2563 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>2564 ret <8 x i16> %tmp12565}2566 2567define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {2568; CHECK-SD-LABEL: orr16imm4s_lsl16:2569; CHECK-SD: // %bb.0:2570; CHECK-SD-NEXT: orr v0.4s, #255, lsl #162571; CHECK-SD-NEXT: ret2572;2573; CHECK-GI-LABEL: orr16imm4s_lsl16:2574; CHECK-GI: // %bb.0:2575; CHECK-GI-NEXT: adrp x8, .LCPI166_02576; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI166_0]2577; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2578; CHECK-GI-NEXT: ret2579 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>2580 ret <8 x i16> %tmp12581}2582 2583define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {2584; CHECK-SD-LABEL: orr16imm4s_lsl24:2585; CHECK-SD: // %bb.0:2586; CHECK-SD-NEXT: orr v0.4s, #255, lsl #242587; CHECK-SD-NEXT: ret2588;2589; CHECK-GI-LABEL: orr16imm4s_lsl24:2590; CHECK-GI: // %bb.0:2591; CHECK-GI-NEXT: adrp x8, .LCPI167_02592; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI167_0]2593; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2594; CHECK-GI-NEXT: ret2595 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>2596 ret <8 x i16> %tmp12597}2598 2599define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {2600; CHECK-SD-LABEL: orr64imm4s_lsl0:2601; CHECK-SD: // %bb.0:2602; CHECK-SD-NEXT: orr v0.4s, #2552603; CHECK-SD-NEXT: ret2604;2605; CHECK-GI-LABEL: orr64imm4s_lsl0:2606; CHECK-GI: // %bb.0:2607; CHECK-GI-NEXT: movi v1.2d, #0x0000ff000000ff2608; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2609; CHECK-GI-NEXT: ret2610 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>2611 ret <2 x i64> %tmp12612}2613 2614define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {2615; CHECK-SD-LABEL: orr64imm4s_lsl8:2616; CHECK-SD: // %bb.0:2617; CHECK-SD-NEXT: orr v0.4s, #255, lsl #82618; CHECK-SD-NEXT: ret2619;2620; CHECK-GI-LABEL: orr64imm4s_lsl8:2621; CHECK-GI: // %bb.0:2622; CHECK-GI-NEXT: movi v1.2d, #0x00ff000000ff002623; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2624; CHECK-GI-NEXT: ret2625 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>2626 ret <2 x i64> %tmp12627}2628 2629define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {2630; CHECK-SD-LABEL: orr64imm4s_lsl16:2631; CHECK-SD: // %bb.0:2632; CHECK-SD-NEXT: orr v0.4s, #255, lsl #162633; CHECK-SD-NEXT: ret2634;2635; CHECK-GI-LABEL: orr64imm4s_lsl16:2636; CHECK-GI: // %bb.0:2637; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff00002638; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2639; CHECK-GI-NEXT: ret2640 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>2641 ret <2 x i64> %tmp12642}2643 2644define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {2645; CHECK-SD-LABEL: orr64imm4s_lsl24:2646; CHECK-SD: // %bb.0:2647; CHECK-SD-NEXT: orr v0.4s, #255, lsl #242648; CHECK-SD-NEXT: ret2649;2650; CHECK-GI-LABEL: orr64imm4s_lsl24:2651; CHECK-GI: // %bb.0:2652; CHECK-GI-NEXT: movi v1.2d, #0xff000000ff0000002653; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2654; CHECK-GI-NEXT: ret2655 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>2656 ret <2 x i64> %tmp12657}2658 2659define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {2660; CHECK-SD-LABEL: orr8imm4h_lsl0:2661; CHECK-SD: // %bb.0:2662; CHECK-SD-NEXT: orr v0.4h, #2552663; CHECK-SD-NEXT: ret2664;2665; CHECK-GI-LABEL: orr8imm4h_lsl0:2666; CHECK-GI: // %bb.0:2667; CHECK-GI-NEXT: adrp x8, .LCPI172_02668; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI172_0]2669; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2670; CHECK-GI-NEXT: ret2671 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>2672 ret <8 x i8> %tmp12673}2674 2675define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {2676; CHECK-SD-LABEL: orr8imm4h_lsl8:2677; CHECK-SD: // %bb.0:2678; CHECK-SD-NEXT: orr v0.4h, #255, lsl #82679; CHECK-SD-NEXT: ret2680;2681; CHECK-GI-LABEL: orr8imm4h_lsl8:2682; CHECK-GI: // %bb.0:2683; CHECK-GI-NEXT: adrp x8, .LCPI173_02684; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI173_0]2685; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2686; CHECK-GI-NEXT: ret2687 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>2688 ret <8 x i8> %tmp12689}2690 2691define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {2692; CHECK-SD-LABEL: orr16imm4h_lsl0:2693; CHECK-SD: // %bb.0:2694; CHECK-SD-NEXT: orr v0.4h, #2552695; CHECK-SD-NEXT: ret2696;2697; CHECK-GI-LABEL: orr16imm4h_lsl0:2698; CHECK-GI: // %bb.0:2699; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff2700; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2701; CHECK-GI-NEXT: ret2702 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>2703 ret <2 x i32> %tmp12704}2705 2706define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {2707; CHECK-SD-LABEL: orr16imm4h_lsl8:2708; CHECK-SD: // %bb.0:2709; CHECK-SD-NEXT: orr v0.4h, #255, lsl #82710; CHECK-SD-NEXT: ret2711;2712; CHECK-GI-LABEL: orr16imm4h_lsl8:2713; CHECK-GI: // %bb.0:2714; CHECK-GI-NEXT: movi d1, #0xff00ff00ff00ff002715; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2716; CHECK-GI-NEXT: ret2717 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>2718 ret <2 x i32> %tmp12719}2720 2721define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {2722; CHECK-SD-LABEL: orr64imm4h_lsl0:2723; CHECK-SD: // %bb.0:2724; CHECK-SD-NEXT: orr v0.4h, #2552725; CHECK-SD-NEXT: ret2726;2727; CHECK-GI-LABEL: orr64imm4h_lsl0:2728; CHECK-GI: // %bb.0:2729; CHECK-GI-NEXT: fmov x8, d02730; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff2731; CHECK-GI-NEXT: fmov d0, x82732; CHECK-GI-NEXT: ret2733 %tmp1 = or <1 x i64> %a, < i64 71777214294589695>2734 ret <1 x i64> %tmp12735}2736 2737define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {2738; CHECK-SD-LABEL: orr64imm4h_lsl8:2739; CHECK-SD: // %bb.0:2740; CHECK-SD-NEXT: orr v0.4h, #255, lsl #82741; CHECK-SD-NEXT: ret2742;2743; CHECK-GI-LABEL: orr64imm4h_lsl8:2744; CHECK-GI: // %bb.0:2745; CHECK-GI-NEXT: fmov x8, d02746; CHECK-GI-NEXT: orr x8, x8, #0xff00ff00ff00ff002747; CHECK-GI-NEXT: fmov d0, x82748; CHECK-GI-NEXT: ret2749 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696>2750 ret <1 x i64> %tmp12751}2752 2753define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {2754; CHECK-SD-LABEL: orr8imm8h_lsl0:2755; CHECK-SD: // %bb.0:2756; CHECK-SD-NEXT: orr v0.8h, #2552757; CHECK-SD-NEXT: ret2758;2759; CHECK-GI-LABEL: orr8imm8h_lsl0:2760; CHECK-GI: // %bb.0:2761; CHECK-GI-NEXT: adrp x8, .LCPI178_02762; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI178_0]2763; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2764; CHECK-GI-NEXT: ret2765 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>2766 ret <16 x i8> %tmp12767}2768 2769define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {2770; CHECK-SD-LABEL: orr8imm8h_lsl8:2771; CHECK-SD: // %bb.0:2772; CHECK-SD-NEXT: orr v0.8h, #255, lsl #82773; CHECK-SD-NEXT: ret2774;2775; CHECK-GI-LABEL: orr8imm8h_lsl8:2776; CHECK-GI: // %bb.0:2777; CHECK-GI-NEXT: adrp x8, .LCPI179_02778; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI179_0]2779; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2780; CHECK-GI-NEXT: ret2781 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>2782 ret <16 x i8> %tmp12783}2784 2785define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {2786; CHECK-SD-LABEL: orr16imm8h_lsl0:2787; CHECK-SD: // %bb.0:2788; CHECK-SD-NEXT: orr v0.8h, #2552789; CHECK-SD-NEXT: ret2790;2791; CHECK-GI-LABEL: orr16imm8h_lsl0:2792; CHECK-GI: // %bb.0:2793; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff2794; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2795; CHECK-GI-NEXT: ret2796 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>2797 ret <4 x i32> %tmp12798}2799 2800define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {2801; CHECK-SD-LABEL: orr16imm8h_lsl8:2802; CHECK-SD: // %bb.0:2803; CHECK-SD-NEXT: orr v0.8h, #255, lsl #82804; CHECK-SD-NEXT: ret2805;2806; CHECK-GI-LABEL: orr16imm8h_lsl8:2807; CHECK-GI: // %bb.0:2808; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff002809; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2810; CHECK-GI-NEXT: ret2811 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>2812 ret <4 x i32> %tmp12813}2814 2815define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {2816; CHECK-SD-LABEL: orr64imm8h_lsl0:2817; CHECK-SD: // %bb.0:2818; CHECK-SD-NEXT: orr v0.8h, #2552819; CHECK-SD-NEXT: ret2820;2821; CHECK-GI-LABEL: orr64imm8h_lsl0:2822; CHECK-GI: // %bb.0:2823; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff2824; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2825; CHECK-GI-NEXT: ret2826 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>2827 ret <2 x i64> %tmp12828}2829 2830define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {2831; CHECK-SD-LABEL: orr64imm8h_lsl8:2832; CHECK-SD: // %bb.0:2833; CHECK-SD-NEXT: orr v0.8h, #255, lsl #82834; CHECK-SD-NEXT: ret2835;2836; CHECK-GI-LABEL: orr64imm8h_lsl8:2837; CHECK-GI: // %bb.0:2838; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff002839; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2840; CHECK-GI-NEXT: ret2841 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>2842 ret <2 x i64> %tmp12843}2844 2845define <8 x i16> @pr149380(<4 x i16> %u1, <1 x i64> %u2, <8 x i16> %vqshlu_n169) {2846; CHECK-SD-LABEL: pr149380:2847; CHECK-SD: // %bb.0: // %entry2848; CHECK-SD-NEXT: movi v0.8h, #12849; CHECK-SD-NEXT: orr v2.8h, #12850; CHECK-SD-NEXT: sqadd v0.8h, v2.8h, v0.8h2851; CHECK-SD-NEXT: ret2852;2853; CHECK-GI-LABEL: pr149380:2854; CHECK-GI: // %bb.0: // %entry2855; CHECK-GI-NEXT: movi v0.2d, #0xffffffffffffffff2856; CHECK-GI-NEXT: neg v1.8h, v2.8h2857; CHECK-GI-NEXT: movi v3.8h, #12858; CHECK-GI-NEXT: neg v1.8h, v1.8h2859; CHECK-GI-NEXT: sub v0.8h, v0.8h, v2.8h2860; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b2861; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b2862; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b2863; CHECK-GI-NEXT: sqadd v0.8h, v3.8h, v0.8h2864; CHECK-GI-NEXT: ret2865entry:2866 %mul.i = mul <8 x i16> %vqshlu_n169, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >2867 %sub.i = sub <8 x i16> zeroinitializer, %mul.i2868 %vbsl3.i = and <8 x i16> %sub.i, %vqshlu_n1692869 %0 = add <8 x i16> %mul.i, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >2870 %vbsl4.i = and <8 x i16> %0, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 >2871 %vbsl5.i = or <8 x i16> %vbsl3.i, %vbsl4.i2872 %vqaddq_v2.i26515 = tail call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 >, <8 x i16> %vbsl5.i)2873 ret <8 x i16> %vqaddq_v2.i265152874}2875