344 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple aarch64 -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple aarch64 -o - -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <8 x i32> @extmuls_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {6; CHECK-SD-LABEL: extmuls_v8i8_i32:7; CHECK-SD: // %bb.0: // %entry8; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b9; CHECK-SD-NEXT: sshll2 v1.4s, v0.8h, #010; CHECK-SD-NEXT: sshll v0.4s, v0.4h, #011; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: extmuls_v8i8_i32:14; CHECK-GI: // %bb.0: // %entry15; CHECK-GI-NEXT: smull v1.8h, v0.8b, v1.8b16; CHECK-GI-NEXT: sshll v0.4s, v1.4h, #017; CHECK-GI-NEXT: sshll2 v1.4s, v1.8h, #018; CHECK-GI-NEXT: ret19entry:20 %s0s = sext <8 x i8> %s0 to <8 x i32>21 %s1s = sext <8 x i8> %s1 to <8 x i32>22 %m = mul <8 x i32> %s0s, %s1s23 ret <8 x i32> %m24}25 26define <8 x i32> @extmulu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {27; CHECK-SD-LABEL: extmulu_v8i8_i32:28; CHECK-SD: // %bb.0: // %entry29; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b30; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #031; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #032; CHECK-SD-NEXT: ret33;34; CHECK-GI-LABEL: extmulu_v8i8_i32:35; CHECK-GI: // %bb.0: // %entry36; CHECK-GI-NEXT: umull v1.8h, v0.8b, v1.8b37; CHECK-GI-NEXT: ushll v0.4s, v1.4h, #038; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #039; CHECK-GI-NEXT: ret40entry:41 %s0s = zext <8 x i8> %s0 to <8 x i32>42 %s1s = zext <8 x i8> %s1 to <8 x i32>43 %m = mul <8 x i32> %s0s, %s1s44 ret <8 x i32> %m45}46 47define <8 x i32> @extmulsu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1) {48; CHECK-SD-LABEL: extmulsu_v8i8_i32:49; CHECK-SD: // %bb.0: // %entry50; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #051; CHECK-SD-NEXT: ushll v2.8h, v1.8b, #052; CHECK-SD-NEXT: smull2 v1.4s, v0.8h, v2.8h53; CHECK-SD-NEXT: smull v0.4s, v0.4h, v2.4h54; CHECK-SD-NEXT: ret55;56; CHECK-GI-LABEL: extmulsu_v8i8_i32:57; CHECK-GI: // %bb.0: // %entry58; CHECK-GI-NEXT: sshll v2.8h, v0.8b, #059; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #060; CHECK-GI-NEXT: smull v0.4s, v2.4h, v1.4h61; CHECK-GI-NEXT: smull2 v1.4s, v2.8h, v1.8h62; CHECK-GI-NEXT: ret63entry:64 %s0s = sext <8 x i8> %s0 to <8 x i32>65 %s1s = zext <8 x i8> %s1 to <8 x i32>66 %m = mul <8 x i32> %s0s, %s1s67 ret <8 x i32> %m68}69 70define <8 x i32> @extmuladds_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1, <8 x i32> %b) {71; CHECK-SD-LABEL: extmuladds_v8i8_i32:72; CHECK-SD: // %bb.0: // %entry73; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b74; CHECK-SD-NEXT: saddw2 v1.4s, v3.4s, v0.8h75; CHECK-SD-NEXT: saddw v0.4s, v2.4s, v0.4h76; CHECK-SD-NEXT: ret77;78; CHECK-GI-LABEL: extmuladds_v8i8_i32:79; CHECK-GI: // %bb.0: // %entry80; CHECK-GI-NEXT: smull v1.8h, v0.8b, v1.8b81; CHECK-GI-NEXT: saddw v0.4s, v2.4s, v1.4h82; CHECK-GI-NEXT: saddw2 v1.4s, v3.4s, v1.8h83; CHECK-GI-NEXT: ret84entry:85 %s0s = sext <8 x i8> %s0 to <8 x i32>86 %s1s = sext <8 x i8> %s1 to <8 x i32>87 %m = mul <8 x i32> %s0s, %s1s88 %a = add <8 x i32> %m, %b89 ret <8 x i32> %a90}91 92define <8 x i32> @extmuladdu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1, <8 x i32> %b) {93; CHECK-SD-LABEL: extmuladdu_v8i8_i32:94; CHECK-SD: // %bb.0: // %entry95; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b96; CHECK-SD-NEXT: uaddw2 v1.4s, v3.4s, v0.8h97; CHECK-SD-NEXT: uaddw v0.4s, v2.4s, v0.4h98; CHECK-SD-NEXT: ret99;100; CHECK-GI-LABEL: extmuladdu_v8i8_i32:101; CHECK-GI: // %bb.0: // %entry102; CHECK-GI-NEXT: umull v1.8h, v0.8b, v1.8b103; CHECK-GI-NEXT: uaddw v0.4s, v2.4s, v1.4h104; CHECK-GI-NEXT: uaddw2 v1.4s, v3.4s, v1.8h105; CHECK-GI-NEXT: ret106entry:107 %s0s = zext <8 x i8> %s0 to <8 x i32>108 %s1s = zext <8 x i8> %s1 to <8 x i32>109 %m = mul <8 x i32> %s0s, %s1s110 %a = add <8 x i32> %m, %b111 ret <8 x i32> %a112}113 114define <8 x i32> @extmuladdsu_v8i8_i32(<8 x i8> %s0, <8 x i8> %s1, <8 x i32> %b) {115; CHECK-SD-LABEL: extmuladdsu_v8i8_i32:116; CHECK-SD: // %bb.0: // %entry117; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0118; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0119; CHECK-SD-NEXT: smlal2 v3.4s, v0.8h, v1.8h120; CHECK-SD-NEXT: smlal v2.4s, v0.4h, v1.4h121; CHECK-SD-NEXT: mov v0.16b, v2.16b122; CHECK-SD-NEXT: mov v1.16b, v3.16b123; CHECK-SD-NEXT: ret124;125; CHECK-GI-LABEL: extmuladdsu_v8i8_i32:126; CHECK-GI: // %bb.0: // %entry127; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0128; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0129; CHECK-GI-NEXT: smlal v2.4s, v0.4h, v1.4h130; CHECK-GI-NEXT: smlal2 v3.4s, v0.8h, v1.8h131; CHECK-GI-NEXT: mov v0.16b, v2.16b132; CHECK-GI-NEXT: mov v1.16b, v3.16b133; CHECK-GI-NEXT: ret134entry:135 %s0s = sext <8 x i8> %s0 to <8 x i32>136 %s1s = zext <8 x i8> %s1 to <8 x i32>137 %m = mul <8 x i32> %s0s, %s1s138 %a = add <8 x i32> %m, %b139 ret <8 x i32> %a140}141 142 143 144define <8 x i64> @extmuls_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {145; CHECK-SD-LABEL: extmuls_v8i8_i64:146; CHECK-SD: // %bb.0: // %entry147; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b148; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0149; CHECK-SD-NEXT: sshll2 v2.4s, v0.8h, #0150; CHECK-SD-NEXT: sshll v0.2d, v1.2s, #0151; CHECK-SD-NEXT: sshll2 v3.2d, v2.4s, #0152; CHECK-SD-NEXT: sshll2 v1.2d, v1.4s, #0153; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0154; CHECK-SD-NEXT: ret155;156; CHECK-GI-LABEL: extmuls_v8i8_i64:157; CHECK-GI: // %bb.0: // %entry158; CHECK-GI-NEXT: smull v0.8h, v0.8b, v1.8b159; CHECK-GI-NEXT: sshll v1.4s, v0.4h, #0160; CHECK-GI-NEXT: sshll2 v3.4s, v0.8h, #0161; CHECK-GI-NEXT: sshll v0.2d, v1.2s, #0162; CHECK-GI-NEXT: sshll2 v1.2d, v1.4s, #0163; CHECK-GI-NEXT: sshll v2.2d, v3.2s, #0164; CHECK-GI-NEXT: sshll2 v3.2d, v3.4s, #0165; CHECK-GI-NEXT: ret166entry:167 %s0s = sext <8 x i8> %s0 to <8 x i64>168 %s1s = sext <8 x i8> %s1 to <8 x i64>169 %m = mul <8 x i64> %s0s, %s1s170 ret <8 x i64> %m171}172 173define <8 x i64> @extmulu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {174; CHECK-SD-LABEL: extmulu_v8i8_i64:175; CHECK-SD: // %bb.0: // %entry176; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b177; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0178; CHECK-SD-NEXT: ushll2 v2.4s, v0.8h, #0179; CHECK-SD-NEXT: ushll v0.2d, v1.2s, #0180; CHECK-SD-NEXT: ushll2 v3.2d, v2.4s, #0181; CHECK-SD-NEXT: ushll2 v1.2d, v1.4s, #0182; CHECK-SD-NEXT: ushll v2.2d, v2.2s, #0183; CHECK-SD-NEXT: ret184;185; CHECK-GI-LABEL: extmulu_v8i8_i64:186; CHECK-GI: // %bb.0: // %entry187; CHECK-GI-NEXT: umull v0.8h, v0.8b, v1.8b188; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0189; CHECK-GI-NEXT: ushll2 v3.4s, v0.8h, #0190; CHECK-GI-NEXT: ushll v0.2d, v1.2s, #0191; CHECK-GI-NEXT: ushll2 v1.2d, v1.4s, #0192; CHECK-GI-NEXT: ushll v2.2d, v3.2s, #0193; CHECK-GI-NEXT: ushll2 v3.2d, v3.4s, #0194; CHECK-GI-NEXT: ret195entry:196 %s0s = zext <8 x i8> %s0 to <8 x i64>197 %s1s = zext <8 x i8> %s1 to <8 x i64>198 %m = mul <8 x i64> %s0s, %s1s199 ret <8 x i64> %m200}201 202define <8 x i64> @extaddsu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1) {203; CHECK-SD-LABEL: extaddsu_v8i8_i64:204; CHECK-SD: // %bb.0: // %entry205; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0206; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0207; CHECK-SD-NEXT: sshll v2.4s, v0.4h, #0208; CHECK-SD-NEXT: ushll v4.4s, v1.4h, #0209; CHECK-SD-NEXT: sshll2 v5.4s, v0.8h, #0210; CHECK-SD-NEXT: ushll2 v6.4s, v1.8h, #0211; CHECK-SD-NEXT: smull v0.2d, v2.2s, v4.2s212; CHECK-SD-NEXT: smull2 v1.2d, v2.4s, v4.4s213; CHECK-SD-NEXT: smull2 v3.2d, v5.4s, v6.4s214; CHECK-SD-NEXT: smull v2.2d, v5.2s, v6.2s215; CHECK-SD-NEXT: ret216;217; CHECK-GI-LABEL: extaddsu_v8i8_i64:218; CHECK-GI: // %bb.0: // %entry219; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0220; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0221; CHECK-GI-NEXT: sshll v2.4s, v0.4h, #0222; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0223; CHECK-GI-NEXT: sshll2 v4.4s, v0.8h, #0224; CHECK-GI-NEXT: ushll2 v5.4s, v1.8h, #0225; CHECK-GI-NEXT: smull v0.2d, v2.2s, v3.2s226; CHECK-GI-NEXT: smull2 v1.2d, v2.4s, v3.4s227; CHECK-GI-NEXT: smull v2.2d, v4.2s, v5.2s228; CHECK-GI-NEXT: smull2 v3.2d, v4.4s, v5.4s229; CHECK-GI-NEXT: ret230entry:231 %s0s = sext <8 x i8> %s0 to <8 x i64>232 %s1s = zext <8 x i8> %s1 to <8 x i64>233 %m = mul <8 x i64> %s0s, %s1s234 ret <8 x i64> %m235}236 237define <8 x i64> @extmuladds_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1, <8 x i64> %b) {238; CHECK-SD-LABEL: extmuladds_v8i8_i64:239; CHECK-SD: // %bb.0: // %entry240; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b241; CHECK-SD-NEXT: sshll2 v6.4s, v0.8h, #0242; CHECK-SD-NEXT: sshll v1.4s, v0.4h, #0243; CHECK-SD-NEXT: saddw2 v5.2d, v5.2d, v6.4s244; CHECK-SD-NEXT: saddw v0.2d, v2.2d, v1.2s245; CHECK-SD-NEXT: saddw2 v1.2d, v3.2d, v1.4s246; CHECK-SD-NEXT: saddw v2.2d, v4.2d, v6.2s247; CHECK-SD-NEXT: mov v3.16b, v5.16b248; CHECK-SD-NEXT: ret249;250; CHECK-GI-LABEL: extmuladds_v8i8_i64:251; CHECK-GI: // %bb.0: // %entry252; CHECK-GI-NEXT: smull v0.8h, v0.8b, v1.8b253; CHECK-GI-NEXT: sshll v1.4s, v0.4h, #0254; CHECK-GI-NEXT: sshll2 v6.4s, v0.8h, #0255; CHECK-GI-NEXT: saddw v0.2d, v2.2d, v1.2s256; CHECK-GI-NEXT: saddw2 v1.2d, v3.2d, v1.4s257; CHECK-GI-NEXT: saddw v2.2d, v4.2d, v6.2s258; CHECK-GI-NEXT: saddw2 v3.2d, v5.2d, v6.4s259; CHECK-GI-NEXT: ret260entry:261 %s0s = sext <8 x i8> %s0 to <8 x i64>262 %s1s = sext <8 x i8> %s1 to <8 x i64>263 %m = mul <8 x i64> %s0s, %s1s264 %a = add <8 x i64> %m, %b265 ret <8 x i64> %a266}267 268define <8 x i64> @extmuladdu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1, <8 x i64> %b) {269; CHECK-SD-LABEL: extmuladdu_v8i8_i64:270; CHECK-SD: // %bb.0: // %entry271; CHECK-SD-NEXT: umull v0.8h, v0.8b, v1.8b272; CHECK-SD-NEXT: ushll2 v6.4s, v0.8h, #0273; CHECK-SD-NEXT: ushll v1.4s, v0.4h, #0274; CHECK-SD-NEXT: uaddw2 v5.2d, v5.2d, v6.4s275; CHECK-SD-NEXT: uaddw v0.2d, v2.2d, v1.2s276; CHECK-SD-NEXT: uaddw2 v1.2d, v3.2d, v1.4s277; CHECK-SD-NEXT: uaddw v2.2d, v4.2d, v6.2s278; CHECK-SD-NEXT: mov v3.16b, v5.16b279; CHECK-SD-NEXT: ret280;281; CHECK-GI-LABEL: extmuladdu_v8i8_i64:282; CHECK-GI: // %bb.0: // %entry283; CHECK-GI-NEXT: umull v0.8h, v0.8b, v1.8b284; CHECK-GI-NEXT: ushll v1.4s, v0.4h, #0285; CHECK-GI-NEXT: ushll2 v6.4s, v0.8h, #0286; CHECK-GI-NEXT: uaddw v0.2d, v2.2d, v1.2s287; CHECK-GI-NEXT: uaddw2 v1.2d, v3.2d, v1.4s288; CHECK-GI-NEXT: uaddw v2.2d, v4.2d, v6.2s289; CHECK-GI-NEXT: uaddw2 v3.2d, v5.2d, v6.4s290; CHECK-GI-NEXT: ret291entry:292 %s0s = zext <8 x i8> %s0 to <8 x i64>293 %s1s = zext <8 x i8> %s1 to <8 x i64>294 %m = mul <8 x i64> %s0s, %s1s295 %a = add <8 x i64> %m, %b296 ret <8 x i64> %a297}298 299define <8 x i64> @extmuladdsu_v8i8_i64(<8 x i8> %s0, <8 x i8> %s1, <8 x i64> %b) {300; CHECK-SD-LABEL: extmuladdsu_v8i8_i64:301; CHECK-SD: // %bb.0: // %entry302; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0303; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0304; CHECK-SD-NEXT: sshll v6.4s, v0.4h, #0305; CHECK-SD-NEXT: ushll v7.4s, v1.4h, #0306; CHECK-SD-NEXT: sshll2 v0.4s, v0.8h, #0307; CHECK-SD-NEXT: ushll2 v1.4s, v1.8h, #0308; CHECK-SD-NEXT: smlal v2.2d, v6.2s, v7.2s309; CHECK-SD-NEXT: smlal2 v3.2d, v6.4s, v7.4s310; CHECK-SD-NEXT: smlal2 v5.2d, v0.4s, v1.4s311; CHECK-SD-NEXT: smlal v4.2d, v0.2s, v1.2s312; CHECK-SD-NEXT: mov v0.16b, v2.16b313; CHECK-SD-NEXT: mov v1.16b, v3.16b314; CHECK-SD-NEXT: mov v2.16b, v4.16b315; CHECK-SD-NEXT: mov v3.16b, v5.16b316; CHECK-SD-NEXT: ret317;318; CHECK-GI-LABEL: extmuladdsu_v8i8_i64:319; CHECK-GI: // %bb.0: // %entry320; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0321; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0322; CHECK-GI-NEXT: sshll v6.4s, v0.4h, #0323; CHECK-GI-NEXT: ushll v7.4s, v1.4h, #0324; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0325; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0326; CHECK-GI-NEXT: smlal v2.2d, v6.2s, v7.2s327; CHECK-GI-NEXT: smlal2 v3.2d, v6.4s, v7.4s328; CHECK-GI-NEXT: smlal v4.2d, v0.2s, v1.2s329; CHECK-GI-NEXT: smlal2 v5.2d, v0.4s, v1.4s330; CHECK-GI-NEXT: mov v0.16b, v2.16b331; CHECK-GI-NEXT: mov v1.16b, v3.16b332; CHECK-GI-NEXT: mov v2.16b, v4.16b333; CHECK-GI-NEXT: mov v3.16b, v5.16b334; CHECK-GI-NEXT: ret335entry:336 %s0s = sext <8 x i8> %s0 to <8 x i64>337 %s1s = zext <8 x i8> %s1 to <8 x i64>338 %m = mul <8 x i64> %s0s, %s1s339 %a = add <8 x i64> %m, %b340 ret <8 x i64> %a341}342;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:343; CHECK: {{.*}}344