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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s3 4define <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) {5; CHECK-LABEL: test_vext_s8:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #28; CHECK-NEXT: ret9entry:10 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>11 ret <8 x i8> %vext12}13 14define <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) {15; CHECK-LABEL: test_vext_s16:16; CHECK: // %bb.0: // %entry17; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #618; CHECK-NEXT: ret19entry:20 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>21 ret <4 x i16> %vext22}23 24define <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) {25; CHECK-LABEL: test_vext_s32:26; CHECK: // %bb.0: // %entry27; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #428; CHECK-NEXT: ret29entry:30 %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2>31 ret <2 x i32> %vext32}33 34define <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) {35; CHECK-LABEL: test_vext_s64:36; CHECK: // %bb.0: // %entry37; CHECK-NEXT: ret38entry:39 %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0>40 ret <1 x i64> %vext41}42 43define <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) {44; CHECK-LABEL: test_vextq_s8:45; CHECK: // %bb.0: // %entry46; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #247; CHECK-NEXT: ret48entry:49 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>50 ret <16 x i8> %vext51}52 53define <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) {54; CHECK-LABEL: test_vextq_s16:55; CHECK: // %bb.0: // %entry56; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #657; CHECK-NEXT: ret58entry:59 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>60 ret <8 x i16> %vext61}62 63define <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) {64; CHECK-LABEL: test_vextq_s32:65; CHECK: // %bb.0: // %entry66; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #467; CHECK-NEXT: ret68entry:69 %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>70 ret <4 x i32> %vext71}72 73define <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) {74; CHECK-LABEL: test_vextq_s64:75; CHECK: // %bb.0: // %entry76; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #877; CHECK-NEXT: ret78entry:79 %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>80 ret <2 x i64> %vext81}82 83define <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) {84; CHECK-LABEL: test_vext_u8:85; CHECK: // %bb.0: // %entry86; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #287; CHECK-NEXT: ret88entry:89 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>90 ret <8 x i8> %vext91}92 93define <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) {94; CHECK-LABEL: test_vext_u16:95; CHECK: // %bb.0: // %entry96; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #697; CHECK-NEXT: ret98entry:99 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>100 ret <4 x i16> %vext101}102 103define <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) {104; CHECK-LABEL: test_vext_u32:105; CHECK: // %bb.0: // %entry106; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4107; CHECK-NEXT: ret108entry:109 %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2>110 ret <2 x i32> %vext111}112 113define <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) {114; CHECK-LABEL: test_vext_u64:115; CHECK: // %bb.0: // %entry116; CHECK-NEXT: ret117entry:118 %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0>119 ret <1 x i64> %vext120}121 122define <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) {123; CHECK-LABEL: test_vextq_u8:124; CHECK: // %bb.0: // %entry125; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #2126; CHECK-NEXT: ret127entry:128 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>129 ret <16 x i8> %vext130}131 132define <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) {133; CHECK-LABEL: test_vextq_u16:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #6136; CHECK-NEXT: ret137entry:138 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>139 ret <8 x i16> %vext140}141 142define <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) {143; CHECK-LABEL: test_vextq_u32:144; CHECK: // %bb.0: // %entry145; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4146; CHECK-NEXT: ret147entry:148 %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>149 ret <4 x i32> %vext150}151 152define <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) {153; CHECK-LABEL: test_vextq_u64:154; CHECK: // %bb.0: // %entry155; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8156; CHECK-NEXT: ret157entry:158 %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>159 ret <2 x i64> %vext160}161 162define <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) {163; CHECK-LABEL: test_vext_f32:164; CHECK: // %bb.0: // %entry165; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4166; CHECK-NEXT: ret167entry:168 %vext = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 2>169 ret <2 x float> %vext170}171 172define <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) {173; CHECK-LABEL: test_vext_f64:174; CHECK: // %bb.0: // %entry175; CHECK-NEXT: ret176entry:177 %vext = shufflevector <1 x double> %a, <1 x double> %b, <1 x i32> <i32 0>178 ret <1 x double> %vext179}180 181define <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) {182; CHECK-LABEL: test_vextq_f32:183; CHECK: // %bb.0: // %entry184; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #4185; CHECK-NEXT: ret186entry:187 %vext = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>188 ret <4 x float> %vext189}190 191define <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) {192; CHECK-LABEL: test_vextq_f64:193; CHECK: // %bb.0: // %entry194; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8195; CHECK-NEXT: ret196entry:197 %vext = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>198 ret <2 x double> %vext199}200 201define <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) {202; CHECK-LABEL: test_vext_p8:203; CHECK: // %bb.0: // %entry204; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #2205; CHECK-NEXT: ret206entry:207 %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>208 ret <8 x i8> %vext209}210 211define <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) {212; CHECK-LABEL: test_vext_p16:213; CHECK: // %bb.0: // %entry214; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #6215; CHECK-NEXT: ret216entry:217 %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>218 ret <4 x i16> %vext219}220 221define <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) {222; CHECK-LABEL: test_vextq_p8:223; CHECK: // %bb.0: // %entry224; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #2225; CHECK-NEXT: ret226entry:227 %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>228 ret <16 x i8> %vext229}230 231define <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) {232; CHECK-LABEL: test_vextq_p16:233; CHECK: // %bb.0: // %entry234; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #6235; CHECK-NEXT: ret236entry:237 %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>238 ret <8 x i16> %vext239}240 241define <8 x i8> @test_undef_vext_s8(<8 x i8> %a) {242; CHECK-LABEL: test_undef_vext_s8:243; CHECK: // %bb.0: // %entry244; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #2245; CHECK-NEXT: ret246entry:247 %vext = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 10, i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>248 ret <8 x i8> %vext249}250 251define <16 x i8> @test_undef_vextq_s8(<16 x i8> %a) {252; CHECK-LABEL: test_undef_vextq_s8:253; CHECK: // %bb.0: // %entry254; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #6255; CHECK-NEXT: ret256entry:257 %vext = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 20, i32 20, i32 20, i32 20, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 20, i32 20, i32 20, i32 20, i32 20>258 ret <16 x i8> %vext259}260 261define <4 x i16> @test_undef_vext_s16(<4 x i16> %a) {262; CHECK-LABEL: test_undef_vext_s16:263; CHECK: // %bb.0: // %entry264; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0265; CHECK-NEXT: dup v0.2s, v0.s[1]266; CHECK-NEXT: ret267entry:268 %vext = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>269 ret <4 x i16> %vext270}271 272define <8 x i16> @test_undef_vextq_s16(<8 x i16> %a) {273; CHECK-LABEL: test_undef_vextq_s16:274; CHECK: // %bb.0: // %entry275; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #6276; CHECK-NEXT: ret277entry:278 %vext = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>279 ret <8 x i16> %vext280}281