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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel < %s -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <2 x i64> @v2i64(<2 x i64> %a) {6; CHECK-LABEL: v2i64:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #89; CHECK-NEXT: ret10entry:11 %V128 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 0>12 ret <2 x i64> %V12813}14 15define <2 x ptr> @v2p0(<2 x ptr> %a) {16; CHECK-LABEL: v2p0:17; CHECK: // %bb.0: // %entry18; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #819; CHECK-NEXT: ret20entry:21 %V128 = shufflevector <2 x ptr> %a, <2 x ptr> undef, <2 x i32> <i32 1, i32 0>22 ret <2 x ptr> %V12823}24 25define <4 x i32> @v4i32(<4 x i32> %a) {26; CHECK-LABEL: v4i32:27; CHECK: // %bb.0: // %entry28; CHECK-NEXT: rev64 v0.4s, v0.4s29; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #830; CHECK-NEXT: ret31entry:32 %V128 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>33 ret <4 x i32> %V12834}35 36define <2 x i32> @v2i32(<2 x i32> %a) {37; CHECK-LABEL: v2i32:38; CHECK: // %bb.0: // %entry39; CHECK-NEXT: rev64 v0.2s, v0.2s40; CHECK-NEXT: ret41entry:42 %V128 = shufflevector <2 x i32> %a, <2 x i32> undef, <2 x i32> <i32 1, i32 0>43 ret <2 x i32> %V12844}45 46define <8 x i16> @v8i16(<8 x i16> %a) {47; CHECK-LABEL: v8i16:48; CHECK: // %bb.0: // %entry49; CHECK-NEXT: rev64 v0.8h, v0.8h50; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #851; CHECK-NEXT: ret52entry:53 %V128 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>54 ret <8 x i16> %V12855}56 57define <8 x i16> @v8i16_2(<4 x i16> %a, <4 x i16> %b) {58; CHECK-SD-LABEL: v8i16_2:59; CHECK-SD: // %bb.0: // %entry60; CHECK-SD-NEXT: adrp x8, .LCPI5_061; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q162; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI5_0]63; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q164; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b65; CHECK-SD-NEXT: ret66;67; CHECK-GI-LABEL: v8i16_2:68; CHECK-GI: // %bb.0: // %entry69; CHECK-GI-NEXT: adrp x8, .LCPI5_070; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q171; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI5_0]72; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q173; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b74; CHECK-GI-NEXT: ret75entry:76 %V128 = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>77 ret <8 x i16> %V12878}79 80define <4 x i16> @v8i16_3(<8 x i16> %a) {81; CHECK-SD-LABEL: v8i16_3:82; CHECK-SD: // %bb.0: // %entry83; CHECK-SD-NEXT: rev64 v0.4h, v0.4h84; CHECK-SD-NEXT: ret85;86; CHECK-GI-LABEL: v8i16_3:87; CHECK-GI: // %bb.0: // %entry88; CHECK-GI-NEXT: rev64 v0.8h, v0.8h89; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q090; CHECK-GI-NEXT: ret91entry:92 %V128 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>93 ret <4 x i16> %V12894}95 96define <4 x i16> @v4i16(<4 x i16> %a) {97; CHECK-LABEL: v4i16:98; CHECK: // %bb.0: // %entry99; CHECK-NEXT: rev64 v0.4h, v0.4h100; CHECK-NEXT: ret101entry:102 %V128 = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>103 ret <4 x i16> %V128104}105 106define <16 x i8> @v16i8(<16 x i8> %a) {107; CHECK-LABEL: v16i8:108; CHECK: // %bb.0: // %entry109; CHECK-NEXT: rev64 v0.16b, v0.16b110; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8111; CHECK-NEXT: ret112entry:113 %V128 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>114 ret <16 x i8> %V128115}116 117define <16 x i8> @v16i8_2(<8 x i8> %a, <8 x i8> %b) {118; CHECK-SD-LABEL: v16i8_2:119; CHECK-SD: // %bb.0: // %entry120; CHECK-SD-NEXT: adrp x8, .LCPI9_0121; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1122; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI9_0]123; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1124; CHECK-SD-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b125; CHECK-SD-NEXT: ret126;127; CHECK-GI-LABEL: v16i8_2:128; CHECK-GI: // %bb.0: // %entry129; CHECK-GI-NEXT: adrp x8, .LCPI9_0130; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1131; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI9_0]132; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1133; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b134; CHECK-GI-NEXT: ret135entry:136 %V128 = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>137 ret <16 x i8> %V128138}139 140define <8 x i8> @v8i8(<8 x i8> %a) {141; CHECK-LABEL: v8i8:142; CHECK: // %bb.0: // %entry143; CHECK-NEXT: rev64 v0.8b, v0.8b144; CHECK-NEXT: ret145entry:146 %V128 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>147 ret <8 x i8> %V128148}149 150define <2 x double> @v2f64(<2 x double> %a) {151; CHECK-LABEL: v2f64:152; CHECK: // %bb.0: // %entry153; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8154; CHECK-NEXT: ret155entry:156 %V128 = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> <i32 1, i32 0>157 ret <2 x double> %V128158}159 160define <4 x float> @v4f32(<4 x float> %a) {161; CHECK-LABEL: v4f32:162; CHECK: // %bb.0: // %entry163; CHECK-NEXT: rev64 v0.4s, v0.4s164; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8165; CHECK-NEXT: ret166entry:167 %V128 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>168 ret <4 x float> %V128169}170 171define <2 x float> @v2f32(<2 x float> %a) {172; CHECK-LABEL: v2f32:173; CHECK: // %bb.0: // %entry174; CHECK-NEXT: rev64 v0.2s, v0.2s175; CHECK-NEXT: ret176entry:177 %V128 = shufflevector <2 x float> %a, <2 x float> undef, <2 x i32> <i32 1, i32 0>178 ret <2 x float> %V128179}180 181define <8 x half> @v8f16(<8 x half> %a) {182; CHECK-LABEL: v8f16:183; CHECK: // %bb.0: // %entry184; CHECK-NEXT: rev64 v0.8h, v0.8h185; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8186; CHECK-NEXT: ret187entry:188 %V128 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>189 ret <8 x half> %V128190}191 192define <4 x half> @v4f16(<4 x half> %a) {193; CHECK-LABEL: v4f16:194; CHECK: // %bb.0: // %entry195; CHECK-NEXT: rev64 v0.4h, v0.4h196; CHECK-NEXT: ret197entry:198 %V128 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>199 ret <4 x half> %V128200}201 202define <8 x bfloat> @v8bf16(<8 x bfloat> %a) {203; CHECK-LABEL: v8bf16:204; CHECK: // %bb.0: // %entry205; CHECK-NEXT: rev64 v0.8h, v0.8h206; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8207; CHECK-NEXT: ret208entry:209 %V128 = shufflevector <8 x bfloat> %a, <8 x bfloat> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>210 ret <8 x bfloat> %V128211}212 213define <4 x bfloat> @v4bf16(<4 x bfloat> %a) {214; CHECK-LABEL: v4bf16:215; CHECK: // %bb.0: // %entry216; CHECK-NEXT: rev64 v0.4h, v0.4h217; CHECK-NEXT: ret218entry:219 %V128 = shufflevector <4 x bfloat> %a, <4 x bfloat> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>220 ret <4 x bfloat> %V128221}222