92 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple aarch64-none-linux-gnu < %s | FileCheck %s3 4declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1 immarg)5declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)6 7define i32 @test_sad_v16i8_zext(ptr nocapture readonly %a, ptr nocapture readonly %b) {8; CHECK-LABEL: test_sad_v16i8_zext:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: ldr q0, [x0]11; CHECK-NEXT: ldr q1, [x1]12; CHECK-NEXT: uabdl v2.8h, v1.8b, v0.8b13; CHECK-NEXT: uabal2 v2.8h, v1.16b, v0.16b14; CHECK-NEXT: uaddlv s0, v2.8h15; CHECK-NEXT: fmov w0, s016; CHECK-NEXT: ret17entry:18 %0 = load <16 x i8>, ptr %a19 %1 = zext <16 x i8> %0 to <16 x i32>20 %2 = load <16 x i8>, ptr %b21 %3 = zext <16 x i8> %2 to <16 x i32>22 %4 = sub nsw <16 x i32> %3, %123 %5 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %4, i1 true)24 %6 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %5)25 ret i32 %626}27 28define i32 @test_sad_v16i8_sext(ptr nocapture readonly %a, ptr nocapture readonly %b) {29; CHECK-LABEL: test_sad_v16i8_sext:30; CHECK: // %bb.0: // %entry31; CHECK-NEXT: ldr q0, [x0]32; CHECK-NEXT: ldr q1, [x1]33; CHECK-NEXT: sabdl v2.8h, v1.8b, v0.8b34; CHECK-NEXT: sabal2 v2.8h, v1.16b, v0.16b35; CHECK-NEXT: uaddlv s0, v2.8h36; CHECK-NEXT: fmov w0, s037; CHECK-NEXT: ret38entry:39 %0 = load <16 x i8>, ptr %a40 %1 = sext <16 x i8> %0 to <16 x i32>41 %2 = load <16 x i8>, ptr %b42 %3 = sext <16 x i8> %2 to <16 x i32>43 %4 = sub nsw <16 x i32> %3, %144 %5 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %4, i1 true)45 %6 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %5)46 ret i32 %647}48 49define i32 @test_sad_v16i8_two_step_zext(ptr noundef readonly %a, ptr noundef readonly %b) {50; CHECK-LABEL: test_sad_v16i8_two_step_zext:51; CHECK: // %bb.0: // %entry52; CHECK-NEXT: ldr q0, [x0]53; CHECK-NEXT: ldr q1, [x1]54; CHECK-NEXT: uabdl v2.8h, v1.8b, v0.8b55; CHECK-NEXT: uabal2 v2.8h, v1.16b, v0.16b56; CHECK-NEXT: uaddlv s0, v2.8h57; CHECK-NEXT: fmov w0, s058; CHECK-NEXT: ret59entry:60 %0 = load <16 x i8>, ptr %a61 %1 = zext <16 x i8> %0 to <16 x i16>62 %2 = load <16 x i8>, ptr %b63 %3 = zext <16 x i8> %2 to <16 x i16>64 %4 = sub nsw <16 x i16> %3, %165 %5 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %4, i1 false)66 %6 = zext <16 x i16> %5 to <16 x i32>67 %7 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)68 ret i32 %769}70 71define i32 @test_sad_v16i8_two_step_sext(ptr noundef readonly %a, ptr noundef readonly %b) {72; CHECK-LABEL: test_sad_v16i8_two_step_sext:73; CHECK: // %bb.0: // %entry74; CHECK-NEXT: ldr q0, [x0]75; CHECK-NEXT: ldr q1, [x1]76; CHECK-NEXT: sabdl v2.8h, v1.8b, v0.8b77; CHECK-NEXT: sabal2 v2.8h, v1.16b, v0.16b78; CHECK-NEXT: uaddlv s0, v2.8h79; CHECK-NEXT: fmov w0, s080; CHECK-NEXT: ret81entry:82 %0 = load <16 x i8>, ptr %a83 %1 = sext <16 x i8> %0 to <16 x i16>84 %2 = load <16 x i8>, ptr %b85 %3 = sext <16 x i8> %2 to <16 x i16>86 %4 = sub nsw <16 x i16> %3, %187 %5 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %4, i1 false)88 %6 = zext <16 x i16> %5 to <16 x i32>89 %7 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)90 ret i32 %791}92