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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define <8 x i16> @test_sshll_v8i8(<8 x i8> %a) {6; CHECK-LABEL: test_sshll_v8i8:7; CHECK: // %bb.0:8; CHECK-NEXT: sshll v0.8h, v0.8b, #39; CHECK-NEXT: ret10 %1 = sext <8 x i8> %a to <8 x i16>11 %tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>12 ret <8 x i16> %tmp13}14 15define <8 x i16> @test_sshll_v8i8_big(<8 x i8> %a) {16; CHECK-SD-LABEL: test_sshll_v8i8_big:17; CHECK-SD: // %bb.0:18; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #019; CHECK-SD-NEXT: shl v0.8h, v0.8h, #920; CHECK-SD-NEXT: ret21;22; CHECK-GI-LABEL: test_sshll_v8i8_big:23; CHECK-GI: // %bb.0:24; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #025; CHECK-GI-NEXT: shl v0.8h, v0.8h, #926; CHECK-GI-NEXT: ret27 %1 = sext <8 x i8> %a to <8 x i16>28 %tmp = shl <8 x i16> %1, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>29 ret <8 x i16> %tmp30}31 32define <4 x i32> @test_sshll_v4i16(<4 x i16> %a) {33; CHECK-LABEL: test_sshll_v4i16:34; CHECK: // %bb.0:35; CHECK-NEXT: sshll v0.4s, v0.4h, #936; CHECK-NEXT: ret37 %1 = sext <4 x i16> %a to <4 x i32>38 %tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>39 ret <4 x i32> %tmp40}41 42define <4 x i32> @test_sshll_v4i16_big(<4 x i16> %a) {43; CHECK-SD-LABEL: test_sshll_v4i16_big:44; CHECK-SD: // %bb.0:45; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #046; CHECK-SD-NEXT: shl v0.4s, v0.4s, #1947; CHECK-SD-NEXT: ret48;49; CHECK-GI-LABEL: test_sshll_v4i16_big:50; CHECK-GI: // %bb.0:51; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #052; CHECK-GI-NEXT: shl v0.4s, v0.4s, #1953; CHECK-GI-NEXT: ret54 %1 = sext <4 x i16> %a to <4 x i32>55 %tmp = shl <4 x i32> %1, <i32 19, i32 19, i32 19, i32 19>56 ret <4 x i32> %tmp57}58 59define <2 x i64> @test_sshll_v2i32(<2 x i32> %a) {60; CHECK-LABEL: test_sshll_v2i32:61; CHECK: // %bb.0:62; CHECK-NEXT: sshll v0.2d, v0.2s, #1963; CHECK-NEXT: ret64 %1 = sext <2 x i32> %a to <2 x i64>65 %tmp = shl <2 x i64> %1, <i64 19, i64 19>66 ret <2 x i64> %tmp67}68 69define <2 x i64> @test_sshll_v2i32_big(<2 x i32> %a) {70; CHECK-SD-LABEL: test_sshll_v2i32_big:71; CHECK-SD: // %bb.0:72; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #073; CHECK-SD-NEXT: shl v0.2d, v0.2d, #3674; CHECK-SD-NEXT: ret75;76; CHECK-GI-LABEL: test_sshll_v2i32_big:77; CHECK-GI: // %bb.0:78; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #079; CHECK-GI-NEXT: shl v0.2d, v0.2d, #3680; CHECK-GI-NEXT: ret81 %1 = sext <2 x i32> %a to <2 x i64>82 %tmp = shl <2 x i64> %1, <i64 36, i64 36>83 ret <2 x i64> %tmp84}85 86define <8 x i16> @test_ushll_v8i8(<8 x i8> %a) {87; CHECK-LABEL: test_ushll_v8i8:88; CHECK: // %bb.0:89; CHECK-NEXT: ushll v0.8h, v0.8b, #390; CHECK-NEXT: ret91 %1 = zext <8 x i8> %a to <8 x i16>92 %tmp = shl <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>93 ret <8 x i16> %tmp94}95 96define <8 x i16> @test_ushll_v8i8_big(<8 x i8> %a) {97; CHECK-LABEL: test_ushll_v8i8_big:98; CHECK: // %bb.0:99; CHECK-NEXT: ushll v0.8h, v0.8b, #0100; CHECK-NEXT: shl v0.8h, v0.8h, #9101; CHECK-NEXT: ret102 %1 = zext <8 x i8> %a to <8 x i16>103 %tmp = shl <8 x i16> %1, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>104 ret <8 x i16> %tmp105}106 107define <4 x i32> @test_ushll_v4i16(<4 x i16> %a) {108; CHECK-LABEL: test_ushll_v4i16:109; CHECK: // %bb.0:110; CHECK-NEXT: ushll v0.4s, v0.4h, #9111; CHECK-NEXT: ret112 %1 = zext <4 x i16> %a to <4 x i32>113 %tmp = shl <4 x i32> %1, <i32 9, i32 9, i32 9, i32 9>114 ret <4 x i32> %tmp115}116 117define <4 x i32> @test_ushll_v4i16_big(<4 x i16> %a) {118; CHECK-LABEL: test_ushll_v4i16_big:119; CHECK: // %bb.0:120; CHECK-NEXT: ushll v0.4s, v0.4h, #0121; CHECK-NEXT: shl v0.4s, v0.4s, #19122; CHECK-NEXT: ret123 %1 = zext <4 x i16> %a to <4 x i32>124 %tmp = shl <4 x i32> %1, <i32 19, i32 19, i32 19, i32 19>125 ret <4 x i32> %tmp126}127 128define <2 x i64> @test_ushll_v2i32(<2 x i32> %a) {129; CHECK-LABEL: test_ushll_v2i32:130; CHECK: // %bb.0:131; CHECK-NEXT: ushll v0.2d, v0.2s, #19132; CHECK-NEXT: ret133 %1 = zext <2 x i32> %a to <2 x i64>134 %tmp = shl <2 x i64> %1, <i64 19, i64 19>135 ret <2 x i64> %tmp136}137 138define <2 x i64> @test_ushll_v2i32_big(<2 x i32> %a) {139; CHECK-LABEL: test_ushll_v2i32_big:140; CHECK: // %bb.0:141; CHECK-NEXT: ushll v0.2d, v0.2s, #0142; CHECK-NEXT: shl v0.2d, v0.2d, #36143; CHECK-NEXT: ret144 %1 = zext <2 x i32> %a to <2 x i64>145 %tmp = shl <2 x i64> %1, <i64 36, i64 36>146 ret <2 x i64> %tmp147}148 149define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {150; CHECK-SD-LABEL: test_sshll2_v16i8:151; CHECK-SD: // %bb.0:152; CHECK-SD-NEXT: sshll2 v0.8h, v0.16b, #3153; CHECK-SD-NEXT: ret154;155; CHECK-GI-LABEL: test_sshll2_v16i8:156; CHECK-GI: // %bb.0:157; CHECK-GI-NEXT: mov d0, v0.d[1]158; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #3159; CHECK-GI-NEXT: ret160 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>161 %2 = sext <8 x i8> %1 to <8 x i16>162 %tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>163 ret <8 x i16> %tmp164}165 166define <8 x i16> @test_sshll2_v16i8_big(<16 x i8> %a) {167; CHECK-SD-LABEL: test_sshll2_v16i8_big:168; CHECK-SD: // %bb.0:169; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #0170; CHECK-SD-NEXT: shl v0.8h, v0.8h, #9171; CHECK-SD-NEXT: ret172;173; CHECK-GI-LABEL: test_sshll2_v16i8_big:174; CHECK-GI: // %bb.0:175; CHECK-GI-NEXT: sshll2 v0.8h, v0.16b, #0176; CHECK-GI-NEXT: shl v0.8h, v0.8h, #9177; CHECK-GI-NEXT: ret178 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>179 %2 = sext <8 x i8> %1 to <8 x i16>180 %tmp = shl <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>181 ret <8 x i16> %tmp182}183 184define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {185; CHECK-SD-LABEL: test_sshll2_v8i16:186; CHECK-SD: // %bb.0:187; CHECK-SD-NEXT: sshll2 v0.4s, v0.8h, #9188; CHECK-SD-NEXT: ret189;190; CHECK-GI-LABEL: test_sshll2_v8i16:191; CHECK-GI: // %bb.0:192; CHECK-GI-NEXT: mov d0, v0.d[1]193; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #9194; CHECK-GI-NEXT: ret195 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>196 %2 = sext <4 x i16> %1 to <4 x i32>197 %tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>198 ret <4 x i32> %tmp199}200 201define <4 x i32> @test_sshll2_v8i16_big(<8 x i16> %a) {202; CHECK-SD-LABEL: test_sshll2_v8i16_big:203; CHECK-SD: // %bb.0:204; CHECK-SD-NEXT: ushll2 v0.4s, v0.8h, #0205; CHECK-SD-NEXT: shl v0.4s, v0.4s, #19206; CHECK-SD-NEXT: ret207;208; CHECK-GI-LABEL: test_sshll2_v8i16_big:209; CHECK-GI: // %bb.0:210; CHECK-GI-NEXT: sshll2 v0.4s, v0.8h, #0211; CHECK-GI-NEXT: shl v0.4s, v0.4s, #19212; CHECK-GI-NEXT: ret213 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>214 %2 = sext <4 x i16> %1 to <4 x i32>215 %tmp = shl <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>216 ret <4 x i32> %tmp217}218 219define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {220; CHECK-SD-LABEL: test_sshll2_v4i32:221; CHECK-SD: // %bb.0:222; CHECK-SD-NEXT: sshll2 v0.2d, v0.4s, #19223; CHECK-SD-NEXT: ret224;225; CHECK-GI-LABEL: test_sshll2_v4i32:226; CHECK-GI: // %bb.0:227; CHECK-GI-NEXT: mov d0, v0.d[1]228; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #19229; CHECK-GI-NEXT: ret230 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>231 %2 = sext <2 x i32> %1 to <2 x i64>232 %tmp = shl <2 x i64> %2, <i64 19, i64 19>233 ret <2 x i64> %tmp234}235 236define <2 x i64> @test_sshll2_v4i32_big(<4 x i32> %a) {237; CHECK-SD-LABEL: test_sshll2_v4i32_big:238; CHECK-SD: // %bb.0:239; CHECK-SD-NEXT: ushll2 v0.2d, v0.4s, #0240; CHECK-SD-NEXT: shl v0.2d, v0.2d, #36241; CHECK-SD-NEXT: ret242;243; CHECK-GI-LABEL: test_sshll2_v4i32_big:244; CHECK-GI: // %bb.0:245; CHECK-GI-NEXT: sshll2 v0.2d, v0.4s, #0246; CHECK-GI-NEXT: shl v0.2d, v0.2d, #36247; CHECK-GI-NEXT: ret248 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>249 %2 = sext <2 x i32> %1 to <2 x i64>250 %tmp = shl <2 x i64> %2, <i64 36, i64 36>251 ret <2 x i64> %tmp252}253 254define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {255; CHECK-SD-LABEL: test_ushll2_v16i8:256; CHECK-SD: // %bb.0:257; CHECK-SD-NEXT: ushll2 v0.8h, v0.16b, #3258; CHECK-SD-NEXT: ret259;260; CHECK-GI-LABEL: test_ushll2_v16i8:261; CHECK-GI: // %bb.0:262; CHECK-GI-NEXT: mov d0, v0.d[1]263; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #3264; CHECK-GI-NEXT: ret265 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>266 %2 = zext <8 x i8> %1 to <8 x i16>267 %tmp = shl <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>268 ret <8 x i16> %tmp269}270 271define <8 x i16> @test_ushll2_v16i8_big(<16 x i8> %a) {272; CHECK-LABEL: test_ushll2_v16i8_big:273; CHECK: // %bb.0:274; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0275; CHECK-NEXT: shl v0.8h, v0.8h, #9276; CHECK-NEXT: ret277 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>278 %2 = zext <8 x i8> %1 to <8 x i16>279 %tmp = shl <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>280 ret <8 x i16> %tmp281}282 283define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {284; CHECK-SD-LABEL: test_ushll2_v8i16:285; CHECK-SD: // %bb.0:286; CHECK-SD-NEXT: ushll2 v0.4s, v0.8h, #9287; CHECK-SD-NEXT: ret288;289; CHECK-GI-LABEL: test_ushll2_v8i16:290; CHECK-GI: // %bb.0:291; CHECK-GI-NEXT: mov d0, v0.d[1]292; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #9293; CHECK-GI-NEXT: ret294 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>295 %2 = zext <4 x i16> %1 to <4 x i32>296 %tmp = shl <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9>297 ret <4 x i32> %tmp298}299 300define <4 x i32> @test_ushll2_v8i16_big(<8 x i16> %a) {301; CHECK-LABEL: test_ushll2_v8i16_big:302; CHECK: // %bb.0:303; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0304; CHECK-NEXT: shl v0.4s, v0.4s, #19305; CHECK-NEXT: ret306 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>307 %2 = zext <4 x i16> %1 to <4 x i32>308 %tmp = shl <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19>309 ret <4 x i32> %tmp310}311 312define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {313; CHECK-SD-LABEL: test_ushll2_v4i32:314; CHECK-SD: // %bb.0:315; CHECK-SD-NEXT: ushll2 v0.2d, v0.4s, #19316; CHECK-SD-NEXT: ret317;318; CHECK-GI-LABEL: test_ushll2_v4i32:319; CHECK-GI: // %bb.0:320; CHECK-GI-NEXT: mov d0, v0.d[1]321; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #19322; CHECK-GI-NEXT: ret323 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>324 %2 = zext <2 x i32> %1 to <2 x i64>325 %tmp = shl <2 x i64> %2, <i64 19, i64 19>326 ret <2 x i64> %tmp327}328 329define <2 x i64> @test_ushll2_v4i32_big(<4 x i32> %a) {330; CHECK-LABEL: test_ushll2_v4i32_big:331; CHECK: // %bb.0:332; CHECK-NEXT: ushll2 v0.2d, v0.4s, #0333; CHECK-NEXT: shl v0.2d, v0.2d, #36334; CHECK-NEXT: ret335 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>336 %2 = zext <2 x i32> %1 to <2 x i64>337 %tmp = shl <2 x i64> %2, <i64 36, i64 36>338 ret <2 x i64> %tmp339}340 341define <8 x i16> @test_sshll_shl0_v8i8(<8 x i8> %a) {342; CHECK-LABEL: test_sshll_shl0_v8i8:343; CHECK: // %bb.0:344; CHECK-NEXT: sshll v0.8h, v0.8b, #0345; CHECK-NEXT: ret346 %tmp = sext <8 x i8> %a to <8 x i16>347 ret <8 x i16> %tmp348}349 350define <4 x i32> @test_sshll_shl0_v4i16(<4 x i16> %a) {351; CHECK-LABEL: test_sshll_shl0_v4i16:352; CHECK: // %bb.0:353; CHECK-NEXT: sshll v0.4s, v0.4h, #0354; CHECK-NEXT: ret355 %tmp = sext <4 x i16> %a to <4 x i32>356 ret <4 x i32> %tmp357}358 359define <2 x i64> @test_sshll_shl0_v2i32(<2 x i32> %a) {360; CHECK-LABEL: test_sshll_shl0_v2i32:361; CHECK: // %bb.0:362; CHECK-NEXT: sshll v0.2d, v0.2s, #0363; CHECK-NEXT: ret364 %tmp = sext <2 x i32> %a to <2 x i64>365 ret <2 x i64> %tmp366}367 368define <8 x i16> @test_ushll_shl0_v8i8(<8 x i8> %a) {369; CHECK-LABEL: test_ushll_shl0_v8i8:370; CHECK: // %bb.0:371; CHECK-NEXT: ushll v0.8h, v0.8b, #0372; CHECK-NEXT: ret373 %tmp = zext <8 x i8> %a to <8 x i16>374 ret <8 x i16> %tmp375}376 377define <4 x i32> @test_ushll_shl0_v4i16(<4 x i16> %a) {378; CHECK-LABEL: test_ushll_shl0_v4i16:379; CHECK: // %bb.0:380; CHECK-NEXT: ushll v0.4s, v0.4h, #0381; CHECK-NEXT: ret382 %tmp = zext <4 x i16> %a to <4 x i32>383 ret <4 x i32> %tmp384}385 386define <2 x i64> @test_ushll_shl0_v2i32(<2 x i32> %a) {387; CHECK-LABEL: test_ushll_shl0_v2i32:388; CHECK: // %bb.0:389; CHECK-NEXT: ushll v0.2d, v0.2s, #0390; CHECK-NEXT: ret391 %tmp = zext <2 x i32> %a to <2 x i64>392 ret <2 x i64> %tmp393}394 395define <8 x i16> @test_sshll2_shl0_v16i8(<16 x i8> %a) {396; CHECK-LABEL: test_sshll2_shl0_v16i8:397; CHECK: // %bb.0:398; CHECK-NEXT: sshll2 v0.8h, v0.16b, #0399; CHECK-NEXT: ret400 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>401 %tmp = sext <8 x i8> %1 to <8 x i16>402 ret <8 x i16> %tmp403}404 405define <4 x i32> @test_sshll2_shl0_v8i16(<8 x i16> %a) {406; CHECK-LABEL: test_sshll2_shl0_v8i16:407; CHECK: // %bb.0:408; CHECK-NEXT: sshll2 v0.4s, v0.8h, #0409; CHECK-NEXT: ret410 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>411 %tmp = sext <4 x i16> %1 to <4 x i32>412 ret <4 x i32> %tmp413}414 415define <2 x i64> @test_sshll2_shl0_v4i32(<4 x i32> %a) {416; CHECK-LABEL: test_sshll2_shl0_v4i32:417; CHECK: // %bb.0:418; CHECK-NEXT: sshll2 v0.2d, v0.4s, #0419; CHECK-NEXT: ret420 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>421 %tmp = sext <2 x i32> %1 to <2 x i64>422 ret <2 x i64> %tmp423}424 425define <8 x i16> @test_ushll2_shl0_v16i8(<16 x i8> %a) {426; CHECK-LABEL: test_ushll2_shl0_v16i8:427; CHECK: // %bb.0:428; CHECK-NEXT: ushll2 v0.8h, v0.16b, #0429; CHECK-NEXT: ret430 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>431 %tmp = zext <8 x i8> %1 to <8 x i16>432 ret <8 x i16> %tmp433}434 435define <4 x i32> @test_ushll2_shl0_v8i16(<8 x i16> %a) {436; CHECK-LABEL: test_ushll2_shl0_v8i16:437; CHECK: // %bb.0:438; CHECK-NEXT: ushll2 v0.4s, v0.8h, #0439; CHECK-NEXT: ret440 %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>441 %tmp = zext <4 x i16> %1 to <4 x i32>442 ret <4 x i32> %tmp443}444 445define <2 x i64> @test_ushll2_shl0_v4i32(<4 x i32> %a) {446; CHECK-LABEL: test_ushll2_shl0_v4i32:447; CHECK: // %bb.0:448; CHECK-NEXT: ushll2 v0.2d, v0.4s, #0449; CHECK-NEXT: ret450 %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>451 %tmp = zext <2 x i32> %1 to <2 x i64>452 ret <2 x i64> %tmp453}454 455define <8 x i16> @test_ushll_cmp(<8 x i8> %a, <8 x i8> %b) #0 {456; CHECK-SD-LABEL: test_ushll_cmp:457; CHECK-SD: // %bb.0:458; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b459; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0460; CHECK-SD-NEXT: ret461;462; CHECK-GI-LABEL: test_ushll_cmp:463; CHECK-GI: // %bb.0:464; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b465; CHECK-GI-NEXT: movi v1.2d, #0xff00ff00ff00ff466; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0467; CHECK-GI-NEXT: shl v0.8h, v0.8h, #15468; CHECK-GI-NEXT: cmlt v0.8h, v0.8h, #0469; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b470; CHECK-GI-NEXT: ret471 %cmp.i = icmp eq <8 x i8> %a, %b472 %vcgtz.i.i = sext <8 x i1> %cmp.i to <8 x i8>473 %vmovl.i.i.i = zext <8 x i8> %vcgtz.i.i to <8 x i16>474 ret <8 x i16> %vmovl.i.i.i475}476