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1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=CHECK2 3; LEGAL INTEGER TYPES4 5define <2 x i64> @stepvector_v2i64() {6; CHECK-LABEL: .LCPI0_0:7; CHECK-NEXT: .xword 08; CHECK-NEXT: .xword 19; CHECK-LABEL: stepvector_v2i64:10; CHECK: // %bb.0: // %entry11; CHECK-NEXT: adrp x8, .LCPI0_012; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_0]13; CHECK-NEXT: ret14entry:15 %0 = call <2 x i64> @llvm.stepvector.v2i64()16 ret <2 x i64> %017}18 19define <4 x i32> @stepvector_v4i32() {20; CHECK-LABEL: .LCPI1_0:21; CHECK-NEXT: .word 022; CHECK-NEXT: .word 123; CHECK-NEXT: .word 224; CHECK-NEXT: .word 325; CHECK-LABEL: stepvector_v4i32:26; CHECK: // %bb.0: // %entry27; CHECK-NEXT: adrp x8, .LCPI1_028; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]29; CHECK-NEXT: ret30entry:31 %0 = call <4 x i32> @llvm.stepvector.v4i32()32 ret <4 x i32> %033}34 35define <8 x i16> @stepvector_v8i16() {36; CHECK-LABEL: .LCPI2_0:37; CHECK-NEXT: .hword 038; CHECK-NEXT: .hword 139; CHECK-NEXT: .hword 240; CHECK-NEXT: .hword 341; CHECK-NEXT: .hword 442; CHECK-NEXT: .hword 543; CHECK-NEXT: .hword 644; CHECK-NEXT: .hword 745; CHECK-LABEL: stepvector_v8i16:46; CHECK: // %bb.0: // %entry47; CHECK-NEXT: adrp x8, .LCPI2_048; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI2_0]49; CHECK-NEXT: ret50entry:51 %0 = call <8 x i16> @llvm.stepvector.v8i16()52 ret <8 x i16> %053}54 55define <16 x i8> @stepvector_v16i8() {56; CHECK-LABEL: .LCPI3_0:57; CHECK-NEXT: .byte 058; CHECK-NEXT: .byte 159; CHECK-NEXT: .byte 260; CHECK-NEXT: .byte 361; CHECK-NEXT: .byte 462; CHECK-NEXT: .byte 563; CHECK-NEXT: .byte 664; CHECK-NEXT: .byte 765; CHECK-NEXT: .byte 866; CHECK-NEXT: .byte 967; CHECK-NEXT: .byte 1068; CHECK-NEXT: .byte 1169; CHECK-NEXT: .byte 1270; CHECK-NEXT: .byte 1371; CHECK-NEXT: .byte 1472; CHECK-NEXT: .byte 1573; CHECK-LABEL: stepvector_v16i8:74; CHECK: // %bb.0: // %entry75; CHECK-NEXT: adrp x8, .LCPI3_076; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_0]77; CHECK-NEXT: ret78entry:79 %0 = call <16 x i8> @llvm.stepvector.v16i8()80 ret <16 x i8> %081}82 83; ILLEGAL INTEGER TYPES84 85define <4 x i64> @stepvector_v4i64() {86; CHECK-LABEL: .LCPI4_0:87; CHECK-NEXT: .xword 088; CHECK-NEXT: .xword 189; CHECK-LABEL: .LCPI4_1:90; CHECK-NEXT: .xword 291; CHECK-NEXT: .xword 392; CHECK-LABEL: stepvector_v4i64:93; CHECK: // %bb.0: // %entry94; CHECK-NEXT: adrp x8, .LCPI4_095; CHECK-NEXT: adrp x9, .LCPI4_196; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI4_0]97; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI4_1]98; CHECK-NEXT: ret99entry:100 %0 = call <4 x i64> @llvm.stepvector.v4i64()101 ret <4 x i64> %0102}103 104define <16 x i32> @stepvector_v16i32() {105; CHECK-LABEL: .LCPI5_0:106; CHECK-NEXT: .word 0107; CHECK-NEXT: .word 1108; CHECK-NEXT: .word 2109; CHECK-NEXT: .word 3110; CHECK-LABEL: .LCPI5_1:111; CHECK-NEXT: .word 4112; CHECK-NEXT: .word 5113; CHECK-NEXT: .word 6114; CHECK-NEXT: .word 7115; CHECK-LABEL: .LCPI5_2:116; CHECK-NEXT: .word 8117; CHECK-NEXT: .word 9118; CHECK-NEXT: .word 10119; CHECK-NEXT: .word 11120; CHECK-LABEL: .LCPI5_3:121; CHECK-NEXT: .word 12122; CHECK-NEXT: .word 13123; CHECK-NEXT: .word 14124; CHECK-NEXT: .word 15125; CHECK-LABEL: stepvector_v16i32:126; CHECK: // %bb.0: // %entry127; CHECK-NEXT: adrp x8, .LCPI5_0128; CHECK-NEXT: adrp x9, .LCPI5_1129; CHECK-NEXT: adrp x10, .LCPI5_2130; CHECK-NEXT: adrp x11, .LCPI5_3131; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI5_0]132; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI5_1]133; CHECK-NEXT: ldr q2, [x10, :lo12:.LCPI5_2]134; CHECK-NEXT: ldr q3, [x11, :lo12:.LCPI5_3]135; CHECK-NEXT: ret136entry:137 %0 = call <16 x i32> @llvm.stepvector.v16i32()138 ret <16 x i32> %0139}140 141define <2 x i32> @stepvector_v2i32() {142; CHECK-LABEL: .LCPI6_0:143; CHECK-NEXT: .word 0144; CHECK-NEXT: .word 1145; CHECK-LABEL: stepvector_v2i32:146; CHECK: // %bb.0: // %entry147; CHECK-NEXT: adrp x8, .LCPI6_0148; CHECK-NEXT: ldr d0, [x8, :lo12:.LCPI6_0]149; CHECK-NEXT: ret150entry:151 %0 = call <2 x i32> @llvm.stepvector.v2i32()152 ret <2 x i32> %0153}154 155define <4 x i16> @stepvector_v4i16() {156; CHECK-LABEL: .LCPI7_0:157; CHECK-NEXT: .hword 0158; CHECK-NEXT: .hword 1159; CHECK-NEXT: .hword 2160; CHECK-NEXT: .hword 3161; CHECK-LABEL: stepvector_v4i16:162; CHECK: // %bb.0: // %entry163; CHECK-NEXT: adrp x8, .LCPI7_0164; CHECK-NEXT: ldr d0, [x8, :lo12:.LCPI7_0]165; CHECK-NEXT: ret166entry:167 %0 = call <4 x i16> @llvm.stepvector.v4i16()168 ret <4 x i16> %0169}170 171 172declare <2 x i64> @llvm.stepvector.v2i64()173declare <4 x i32> @llvm.stepvector.v4i32()174declare <8 x i16> @llvm.stepvector.v8i16()175declare <16 x i8> @llvm.stepvector.v16i8()176 177declare <4 x i64> @llvm.stepvector.v4i64()178declare <16 x i32> @llvm.stepvector.v16i32()179declare <2 x i32> @llvm.stepvector.v2i32()180declare <4 x i16> @llvm.stepvector.v4i16()181