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1; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon,+aes | FileCheck %s2 3; This test checks that pmull2 instruction is used for vmull_high_p64 intrinsic.4; There are two extraction operations located in different basic blocks:5;6; %4 = extractelement <2 x i64> %0, i32 17; %12 = extractelement <2 x i64> %9, i32 18;9; They are used by:10;11; @llvm.aarch64.neon.pmull64(i64 %12, i64 %4) #212;13; We test that pattern replacing llvm.aarch64.neon.pmull64 with pmull214; would be applied.15 16; IR for that test was generated from the following .cpp file:17;18; #include <arm_neon.h>19;20; struct SS {21; uint64x2_t x, h;22; };23;24; void func (SS *g, unsigned int count, const unsigned char *buf, poly128_t* res )25; {26; const uint64x2_t x = g->x;27; const uint64x2_t h = g->h;28; uint64x2_t ci = g->x;29;30; for (int i = 0; i < count; i+=2, buf += 16) {31; ci = vreinterpretq_u64_u8(veorq_u8(vreinterpretq_u8_u64(ci),32; vrbitq_u8(vld1q_u8(buf))));33; res[i] = vmull_p64((poly64_t)vget_low_p64(vreinterpretq_p64_u64(ci)),34; (poly64_t)vget_low_p64(vreinterpretq_p64_u64(h)));35; res[i+1] = vmull_high_p64(vreinterpretq_p64_u64(ci),36; vreinterpretq_p64_u64(h));37; }38; }39 40 41;CHECK-LABEL: func:42;CHECK: pmull243 44%struct.SS = type { <2 x i64>, <2 x i64> }45 46; Function Attrs: nofree noinline nounwind47define dso_local void @func(ptr nocapture readonly %g, i32 %count, ptr nocapture readonly %buf, ptr nocapture %res) local_unnamed_addr #0 {48entry:49 %h2 = getelementptr inbounds %struct.SS, ptr %g, i64 0, i32 150 %0 = load <2 x i64>, ptr %h2, align 1651 %cmp34 = icmp eq i32 %count, 052 br i1 %cmp34, label %for.cond.cleanup, label %for.body.lr.ph53 54for.body.lr.ph: ; preds = %entry55 %1 = load <16 x i8>, ptr %g, align 1656 %2 = extractelement <2 x i64> %0, i32 057 %3 = extractelement <2 x i64> %0, i32 158 %4 = zext i32 %count to i6459 br label %for.body60 61for.cond.cleanup: ; preds = %for.body, %entry62 ret void63 64for.body: ; preds = %for.body.lr.ph, %for.body65 %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]66 %buf.addr.036 = phi ptr [ %buf, %for.body.lr.ph ], [ %add.ptr, %for.body ]67 %5 = phi <16 x i8> [ %1, %for.body.lr.ph ], [ %xor.i, %for.body ]68 %6 = load <16 x i8>, ptr %buf.addr.036, align 1669 %vrbit.i = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %6) #070 %xor.i = xor <16 x i8> %vrbit.i, %571 %7 = bitcast <16 x i8> %xor.i to <2 x i64>72 %8 = extractelement <2 x i64> %7, i32 073 %vmull_p64.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %8, i64 %2) #074 %arrayidx = getelementptr inbounds i128, ptr %res, i64 %indvars.iv75 store <16 x i8> %vmull_p64.i, ptr %arrayidx, align 1676 %9 = extractelement <2 x i64> %7, i32 177 %vmull_p64.i.i = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %9, i64 %3) #078 %10 = or i64 %indvars.iv, 179 %arrayidx16 = getelementptr inbounds i128, ptr %res, i64 %1080 store <16 x i8> %vmull_p64.i.i, ptr %arrayidx16, align 1681 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 282 %add.ptr = getelementptr inbounds i8, ptr %buf.addr.036, i64 1683 %cmp = icmp ult i64 %indvars.iv.next, %484 br i1 %cmp, label %for.body, label %for.cond.cleanup 85}86 87; Function Attrs: nounwind readnone88declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) #089 90; Function Attrs: nounwind readnone91declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) #092 93attributes #0 = { nofree noinline nounwind }94