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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s3 4define <4 x half> @shuffle1(<2 x half> %a, <2 x half> %b) {5; CHECK-LABEL: shuffle1:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: zip1 v0.2s, v1.2s, v0.2s8; CHECK-NEXT: ret9entry:10 %res = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 2, i32 3, i32 0, i32 undef>11 ret <4 x half> %res12}13 14define <4 x half> @shuffle2(<2 x half> %a, <2 x half> %b) {15; CHECK-LABEL: shuffle2:16; CHECK: // %bb.0: // %entry17; CHECK-NEXT: zip1 v0.2s, v0.2s, v1.2s18; CHECK-NEXT: ret19entry:20 %res = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 undef, i32 1, i32 2, i32 undef>21 ret <4 x half> %res22}23 24define <4 x i32> @shuffle3(<4 x i32> %a, <4 x i32> %b) {25; CHECK-LABEL: shuffle3:26; CHECK: // %bb.0: // %entry27; CHECK-NEXT: zip2 v0.2d, v1.2d, v0.2d28; CHECK-NEXT: ret29entry:30 %res = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>31 ret <4 x i32> %res32}33 34define <4 x float> @shuffle4(<4 x float> %a, <4 x float> %b) {35; CHECK-LABEL: shuffle4:36; CHECK: // %bb.0: // %entry37; CHECK-NEXT: mov v0.d[1], v1.d[1]38; CHECK-NEXT: ret39entry:40 %res = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>41 ret <4 x float> %res42}43 44define <16 x i8> @shuffle5(<16 x i8> %a, <16 x i8> %b) {45; CHECK-LABEL: shuffle5:46; CHECK: // %bb.0: // %entry47; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h48; CHECK-NEXT: ret49entry:50 %res = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 4, i32 5,51 i32 8, i32 9, i32 12, i32 13,52 i32 16, i32 17, i32 20, i32 21,53 i32 24, i32 25, i32 28, i32 29>54 ret <16 x i8> %res55}56 57define <16 x i8> @shuffle6(<16 x i8> %a, <16 x i8> %b) {58; CHECK-LABEL: shuffle6:59; CHECK: // %bb.0: // %entry60; CHECK-NEXT: trn1 v0.8h, v0.8h, v1.8h61; CHECK-NEXT: ret62entry:63 %res = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17,64 i32 4, i32 5, i32 20, i32 21,65 i32 8, i32 9, i32 24, i32 25,66 i32 12, i32 13, i32 28, i32 29>67 ret <16 x i8> %res68}69 70define <8 x i8> @shuffle7(<8 x i8> %a, <8 x i8> %b) {71; CHECK-LABEL: shuffle7:72; CHECK: // %bb.0: // %entry73; CHECK-NEXT: uzp2 v0.4h, v0.4h, v1.4h74; CHECK-NEXT: ret75entry:76 %res = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 6, i32 undef,77 i32 undef, i32 11, i32 14, i32 undef>78 ret <8 x i8> %res79}80 81define <8 x i8> @shuffle8(<8 x i8> %a, <8 x i8> %b) {82; CHECK-LABEL: shuffle8:83; CHECK: // %bb.0: // %entry84; CHECK-NEXT: trn2 v0.4h, v0.4h, v1.4h85; CHECK-NEXT: ret86entry:87 %res = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 10, i32 undef,88 i32 undef, i32 7, i32 14, i32 undef>89 ret <8 x i8> %res90}91 92; No blocks93define <8 x i8> @shuffle9(<8 x i8> %a) {94; CHECK-LABEL: shuffle9:95; CHECK: // %bb.0:96; CHECK-NEXT: rev32 v0.4h, v0.4h97; CHECK-NEXT: ret98 %res = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 0, i32 1,99 i32 6, i32 7, i32 4, i32 5>100 ret <8 x i8> %res101}102 103define <8 x i16> @shuffle10(<8 x i16> %a) {104; CHECK-LABEL: shuffle10:105; CHECK: // %bb.0:106; CHECK-NEXT: rev64 v0.4s, v0.4s107; CHECK-NEXT: ret108 %res = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 2, i32 3, i32 0, i32 1,109 i32 undef, i32 undef, i32 4, i32 5>110 ret <8 x i16> %res111}112 113define <4 x i16> @shuffle11(<8 x i16> %a, <8 x i16> %b) {114; CHECK-LABEL: shuffle11:115; CHECK: // %bb.0: // %entry116; CHECK-NEXT: zip1 v0.2s, v1.2s, v0.2s117; CHECK-NEXT: ret118entry:119 %res = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 8, i32 9, i32 0, i32 1>120 ret <4 x i16> %res121}122 123define <8 x i8> @shuffle12(<8 x i8> %a, <8 x i8> %b) {124; CHECK-LABEL: shuffle12:125; CHECK: // %bb.0: // %entry126; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h127; CHECK-NEXT: trn2 v0.4h, v0.4h, v0.4h128; CHECK-NEXT: ret129entry:130 %res = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 4, i32 5, i32 4, i32 undef,131 i32 undef, i32 13, i32 12, i32 undef>132 ret <8 x i8> %res133}134 135define <8 x i16> @shuffle_widen_faili1(<4 x i16> %a, <4 x i16> %b) {136; CHECK-LABEL: shuffle_widen_faili1:137; CHECK: // %bb.0: // %entry138; CHECK-NEXT: adrp x8, .LCPI12_0139; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1140; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_0]141; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1142; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b143; CHECK-NEXT: ret144entry:145 %res = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 7, i32 6, i32 0, i32 1,146 i32 3, i32 2, i32 4, i32 5>147 ret <8 x i16> %res148}149 150define <8 x i16> @shuffle_widen_fail2(<4 x i16> %a, <4 x i16> %b) {151; CHECK-LABEL: shuffle_widen_fail2:152; CHECK: // %bb.0: // %entry153; CHECK-NEXT: adrp x8, .LCPI13_0154; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1155; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]156; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1157; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b158; CHECK-NEXT: ret159entry:160 %res = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 6, i32 6, i32 0, i32 1,161 i32 undef, i32 2, i32 4, i32 5>162 ret <8 x i16> %res163}164 165define <8 x i16> @shuffle_widen_fail3(<8 x i16> %a, <8 x i16> %b) {166; CHECK-LABEL: shuffle_widen_fail3:167; CHECK: // %bb.0: // %entry168; CHECK-NEXT: adrp x8, .LCPI14_0169; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1170; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_0]171; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1172; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b173; CHECK-NEXT: ret174entry:175 %res = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 5, i32 12, i32 14,176 i32 10, i32 6, i32 7, i32 13>177 ret <8 x i16> %res178}179