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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 %s -o - | FileCheck %s3 4; The llvm.aarch64_neon_rbit intrinsic should be auto-upgraded to the5; target-independent bitreverse intrinsic.6 7declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) nounwind readnone8 9define <8 x i8> @rbit_8x8(<8 x i8> %A) nounwind {10; CHECK-LABEL: rbit_8x8:11; CHECK: // %bb.0:12; CHECK-NEXT: rbit v0.8b, v0.8b13; CHECK-NEXT: ret14 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %A)15 ret <8 x i8> %tmp316}17 18declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) nounwind readnone19 20define <16 x i8> @rbit_16x8(<16 x i8> %A) nounwind {21; CHECK-LABEL: rbit_16x8:22; CHECK: // %bb.0:23; CHECK-NEXT: rbit v0.16b, v0.16b24; CHECK-NEXT: ret25 %tmp3 = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %A)26 ret <16 x i8> %tmp327}28 29declare <4 x i16> @llvm.aarch64.neon.rbit.v4i16(<4 x i16>) nounwind readnone30 31define <4 x i16> @rbit_4x16(<4 x i16> %A) nounwind {32; CHECK-LABEL: rbit_4x16:33; CHECK: // %bb.0:34; CHECK-NEXT: rev16 v0.8b, v0.8b35; CHECK-NEXT: rbit v0.8b, v0.8b36; CHECK-NEXT: ret37 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rbit.v4i16(<4 x i16> %A)38 ret <4 x i16> %tmp339}40 41declare <8 x i16> @llvm.aarch64.neon.rbit.v8i16(<8 x i16>) nounwind readnone42 43define <8 x i16> @rbit_8x16(<8 x i16> %A) {44; CHECK-LABEL: rbit_8x16:45; CHECK: // %bb.0:46; CHECK-NEXT: rev16 v0.16b, v0.16b47; CHECK-NEXT: rbit v0.16b, v0.16b48; CHECK-NEXT: ret49 %tmp3 = call <8 x i16> @llvm.aarch64.neon.rbit.v8i16(<8 x i16> %A)50 ret <8 x i16> %tmp351}52 53declare <2 x i32> @llvm.aarch64.neon.rbit.v2i32(<2 x i32>) nounwind readnone54 55define <2 x i32> @rbit_2x32(<2 x i32> %A) {56; CHECK-LABEL: rbit_2x32:57; CHECK: // %bb.0:58; CHECK-NEXT: rev32 v0.8b, v0.8b59; CHECK-NEXT: rbit v0.8b, v0.8b60; CHECK-NEXT: ret61 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rbit.v2i32(<2 x i32> %A)62 ret <2 x i32> %tmp363}64 65declare <4 x i32> @llvm.aarch64.neon.rbit.v4i32(<4 x i32>) nounwind readnone66 67define <4 x i32> @rbit_4x32(<4 x i32> %A) {68; CHECK-LABEL: rbit_4x32:69; CHECK: // %bb.0:70; CHECK-NEXT: rev32 v0.16b, v0.16b71; CHECK-NEXT: rbit v0.16b, v0.16b72; CHECK-NEXT: ret73 %tmp3 = call <4 x i32> @llvm.aarch64.neon.rbit.v4i32(<4 x i32> %A)74 ret <4 x i32> %tmp375}76 77declare <1 x i64> @llvm.aarch64.neon.rbit.v1i64(<1 x i64>) readnone78 79define <1 x i64> @rbit_1x64(<1 x i64> %A) {80; CHECK-LABEL: rbit_1x64:81; CHECK: // %bb.0:82; CHECK-NEXT: rev64 v0.8b, v0.8b83; CHECK-NEXT: rbit v0.8b, v0.8b84; CHECK-NEXT: ret85 %tmp3 = call <1 x i64> @llvm.aarch64.neon.rbit.v1i64(<1 x i64> %A)86 ret <1 x i64> %tmp387}88 89declare <2 x i64> @llvm.aarch64.neon.rbit.v2i64(<2 x i64>) readnone90 91define <2 x i64> @rbit_2x64(<2 x i64> %A) {92; CHECK-LABEL: rbit_2x64:93; CHECK: // %bb.0:94; CHECK-NEXT: rev64 v0.16b, v0.16b95; CHECK-NEXT: rbit v0.16b, v0.16b96; CHECK-NEXT: ret97 %tmp3 = call <2 x i64> @llvm.aarch64.neon.rbit.v2i64(<2 x i64> %A)98 ret <2 x i64> %tmp399}100