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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -force-vector-interleave=1 -o - %s | FileCheck %s3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"5target triple = "aarch64-none-unknown-elf"6 7define <4 x i32> @partial_reduce_add_fixed(<4 x i32> %accumulator, <4 x i32> %0) #0 {8; CHECK-LABEL: partial_reduce_add_fixed:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: add v0.4s, v0.4s, v1.4s11; CHECK-NEXT: ret12entry:13 %partial.reduce = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32.v4i32(<4 x i32> %accumulator, <4 x i32> %0)14 ret <4 x i32> %partial.reduce15}16 17define <4 x i32> @partial_reduce_add_fixed_half(<4 x i32> %accumulator, <8 x i32> %0) #0 {18; CHECK-LABEL: partial_reduce_add_fixed_half:19; CHECK: // %bb.0: // %entry20; CHECK-NEXT: add v0.4s, v0.4s, v1.4s21; CHECK-NEXT: add v0.4s, v0.4s, v2.4s22; CHECK-NEXT: ret23entry:24 %partial.reduce = call <4 x i32> @llvm.vector.partial.reduce.add.v4i32.v4i32.v8i32(<4 x i32> %accumulator, <8 x i32> %0)25 ret <4 x i32> %partial.reduce26}27 28define <vscale x 4 x i32> @partial_reduce_add(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0) #0 {29; CHECK-LABEL: partial_reduce_add:30; CHECK: // %bb.0: // %entry31; CHECK-NEXT: add z0.s, z0.s, z1.s32; CHECK-NEXT: ret33entry:34 %partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv4i32(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0)35 ret <vscale x 4 x i32> %partial.reduce36}37 38define <vscale x 4 x i32> @partial_reduce_add_half(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0) #0 {39; CHECK-LABEL: partial_reduce_add_half:40; CHECK: // %bb.0: // %entry41; CHECK-NEXT: add z0.s, z0.s, z1.s42; CHECK-NEXT: add z0.s, z0.s, z2.s43; CHECK-NEXT: ret44entry:45 %partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv8i32(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0)46 ret <vscale x 4 x i32> %partial.reduce47}48 49define <vscale x 4 x i32> @partial_reduce_add_quart(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0) #0 {50; CHECK-LABEL: partial_reduce_add_quart:51; CHECK: // %bb.0: // %entry52; CHECK-NEXT: add z2.s, z2.s, z3.s53; CHECK-NEXT: add z0.s, z0.s, z1.s54; CHECK-NEXT: add z0.s, z0.s, z2.s55; CHECK-NEXT: add z0.s, z0.s, z4.s56; CHECK-NEXT: ret57entry:58 %partial.reduce = call <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv16i32(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0)59 ret <vscale x 4 x i32> %partial.reduce60}61 62define <vscale x 8 x i32> @partial_reduce_add_half_8(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0) #0 {63; CHECK-LABEL: partial_reduce_add_half_8:64; CHECK: // %bb.0: // %entry65; CHECK-NEXT: add z0.s, z0.s, z2.s66; CHECK-NEXT: add z1.s, z1.s, z4.s67; CHECK-NEXT: add z0.s, z0.s, z3.s68; CHECK-NEXT: add z1.s, z1.s, z5.s69; CHECK-NEXT: ret70entry:71 %partial.reduce = call <vscale x 8 x i32> @llvm.vector.partial.reduce.add.nxv8i32.nxv8i32.nxv16i32(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0)72 ret <vscale x 8 x i32> %partial.reduce73}74 75declare <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)76declare <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv8i32(<vscale x 4 x i32>, <vscale x 8 x i32>)77declare <vscale x 4 x i32> @llvm.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv16i32(<vscale x 4 x i32>, <vscale x 16 x i32>)78declare <vscale x 8 x i32> @llvm.vector.partial.reduce.add.nxv8i32.nxv8i32.nxv16i32(<vscale x 8 x i32>, <vscale x 16 x i32>)79 80declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>)81declare i32 @llvm.vector.reduce.add.nxv8i32(<vscale x 8 x i32>)82 83attributes #0 = { "target-features"="+sve2" }84