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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s3 4--- |5 define i64 @loop2(i32 noundef %width) {6 entry:7 %add = add i32 %width, -18 %zext = zext i32 %add to i649 %shl = shl nuw nsw i64 %zext, 110 ret i64 %shl11 }12 13 define <8 x i16> @pr63777(<8 x i16> %vmull.i, ptr %iPtr) {14 entry:15 %ld = load <8 x i8>, ptr %iPtr, align 116 %shuffle.i.i = shufflevector <8 x i8> %ld, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>17 %bc = bitcast <16 x i8> %shuffle.i.i to <8 x i16>18 %vecinit7.i = shufflevector <8 x i16> %bc, <8 x i16> zeroinitializer, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>19 %mul.i109 = mul <8 x i16> %vecinit7.i, %vmull.i20 %or.i = or <8 x i16> %mul.i109, %bc21 ret <8 x i16> %or.i22 }23...24---25---26name: loop227alignment: 428tracksRegLiveness: true29registers:30 - { id: 0, class: gpr32common, preferred-register: '' }31 - { id: 1, class: gpr32common, preferred-register: '' }32 - { id: 2, class: gpr64, preferred-register: '' }33 - { id: 3, class: gpr64all, preferred-register: '' }34 - { id: 4, class: gpr64, preferred-register: '' }35liveins:36 - { reg: '$w0', virtual-reg: '%0' }37body: |38 bb.0.entry:39 liveins: $w040 41 ; CHECK-LABEL: name: loop242 ; CHECK: liveins: $w043 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w045 ; CHECK-NEXT: [[SUBWri:%[0-9]+]]:gpr32common = SUBWri [[COPY]], 1, 046 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF47 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[SUBWri]], %subreg.sub_3248 ; CHECK-NEXT: [[UBFMXri:%[0-9]+]]:gpr64 = nuw nsw UBFMXri killed [[SUBREG_TO_REG]], 63, 3149 ; CHECK-NEXT: $x0 = COPY [[UBFMXri]]50 ; CHECK-NEXT: RET_ReallyLR implicit $x051 %0:gpr32common = COPY $w052 %1:gpr32common = SUBWri %0, 1, 053 %3:gpr64all = IMPLICIT_DEF54 %2:gpr64 = INSERT_SUBREG %3, killed %1, %subreg.sub_3255 %4:gpr64 = nuw nsw UBFMXri killed %2, 63, 3156 $x0 = COPY %457 RET_ReallyLR implicit $x058 59...60---61name: pr6377762tracksRegLiveness: true63registers:64 - { id: 0, class: fpr128, preferred-register: '' }65 - { id: 1, class: gpr64common, preferred-register: '' }66 - { id: 2, class: fpr64, preferred-register: '' }67 - { id: 3, class: fpr128, preferred-register: '' }68 - { id: 4, class: fpr64, preferred-register: '' }69 - { id: 5, class: fpr128, preferred-register: '' }70 - { id: 6, class: fpr128, preferred-register: '' }71 - { id: 7, class: fpr128, preferred-register: '' }72 - { id: 8, class: fpr128, preferred-register: '' }73 - { id: 9, class: fpr128_lo, preferred-register: '' }74 - { id: 10, class: fpr128, preferred-register: '' }75 - { id: 11, class: fpr128, preferred-register: '' }76liveins:77 - { reg: '$q0', virtual-reg: '%0' }78 - { reg: '$x0', virtual-reg: '%1' }79body: |80 bb.0.entry:81 liveins: $q0, $x082 83 ; CHECK-LABEL: name: pr6377784 ; CHECK: liveins: $q0, $x085 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x087 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q088 ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (s64) from %ir.iPtr, align 1)89 ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 090 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub91 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF92 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[COPY2]], %subreg.dsub93 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF94 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128_lo = INSERT_SUBREG [[DEF1]], killed [[LDRDui]], %subreg.dsub95 ; CHECK-NEXT: [[MULv8i16_indexed:%[0-9]+]]:fpr128 = MULv8i16_indexed [[COPY1]], [[INSERT_SUBREG1]], 196 ; CHECK-NEXT: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 killed [[MULv8i16_indexed]], [[INSERT_SUBREG1]]97 ; CHECK-NEXT: $q0 = COPY [[ORRv16i8_]]98 ; CHECK-NEXT: RET_ReallyLR implicit $q099 %1:gpr64common = COPY $x0100 %0:fpr128 = COPY $q0101 %2:fpr64 = LDRDui %1, 0 :: (load (s64) from %ir.iPtr, align 1)102 %3:fpr128 = MOVIv2d_ns 0103 %4:fpr64 = COPY %3.dsub104 %6:fpr128 = IMPLICIT_DEF105 %5:fpr128 = INSERT_SUBREG %6, killed %4, %subreg.dsub106 %8:fpr128 = IMPLICIT_DEF107 %7:fpr128 = INSERT_SUBREG %8, killed %2, %subreg.dsub108 %9:fpr128_lo = INSvi64lane %7, 1, killed %5, 0109 %10:fpr128 = MULv8i16_indexed %0, %9, 1110 %11:fpr128 = ORRv16i8 killed %10, %9111 $q0 = COPY %11112 RET_ReallyLR implicit $q0113 114...115