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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s3 4---5name: removeSxtw6tracksRegLiveness: true7body: |8 bb.0.entry:9 liveins: $x010 ; CHECK-LABEL: name: removeSxtw11 ; CHECK: liveins: $x012 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x014 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_3215 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY1]], 1, 016 ; CHECK-NEXT: $w0 = COPY [[ADDWri]]17 ; CHECK-NEXT: RET_ReallyLR implicit $w018 %0:gpr64 = COPY $x019 %1:gpr64 = SBFMXri %0:gpr64, 0, 3120 %2:gpr32sp = COPY %1.sub_32:gpr6421 %3:gpr32sp = ADDWri %2:gpr32sp, 1, 022 $w0 = COPY %3:gpr32sp23 RET_ReallyLR implicit $w024...25---26name: extraCopy27tracksRegLiveness: true28body: |29 bb.0.entry:30 liveins: $x031 ; CHECK-LABEL: name: extraCopy32 ; CHECK: liveins: $x033 ; CHECK-NEXT: {{ $}}34 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x035 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_3236 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY1]], 1, 037 ; CHECK-NEXT: $w0 = COPY [[ADDWri]]38 ; CHECK-NEXT: RET_ReallyLR implicit $w039 %0:gpr64 = COPY $x040 %1:gpr64 = SBFMXri %0:gpr64, 0, 3141 %2:gpr64all = COPY %1:gpr6442 %3:gpr32sp = COPY %2.sub_32:gpr64all43 %4:gpr32sp = ADDWri %3:gpr32sp, 1, 044 $w0 = COPY %4:gpr32sp45 RET_ReallyLR implicit $w046...47---48name: multipleCopies49tracksRegLiveness: true50body: |51 ; CHECK-LABEL: name: multipleCopies52 ; CHECK: bb.0.entry:53 ; CHECK-NEXT: successors: %bb.1(0x80000000)54 ; CHECK-NEXT: liveins: $w055 ; CHECK-NEXT: {{ $}}56 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w057 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF58 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_3259 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_3260 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr61 ; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY2]], [[COPY1]]62 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBWrr]], %subreg.sub_3263 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: bb.1:65 ; CHECK-NEXT: successors: %bb.2(0x80000000)66 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: bb.2:68 ; CHECK-NEXT: successors: %bb.1(0x04000000), %bb.2(0x7c000000)69 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: CBZX [[SUBREG_TO_REG]], %bb.171 ; CHECK-NEXT: B %bb.272 bb.0.entry:73 successors: %bb.1(0x80000000)74 liveins: $w075 76 %2:gpr32 = COPY $w077 %4:gpr64all = IMPLICIT_DEF78 %3:gpr64 = INSERT_SUBREG %4, %2, %subreg.sub_3279 %5:gpr64 = SBFMXri killed %3, 0, 3180 %0:gpr64all = COPY %581 %6:gpr64all = COPY %082 %7:gpr32 = COPY %6.sub_3283 %8:gpr32 = COPY $wzr84 %9:gpr32 = SUBWrr %8, %785 %10:gpr32 = ORRWrs $wzr, %9, 086 %1:gpr64 = SUBREG_TO_REG 0, %10, %subreg.sub_3287 88 bb.1:89 successors: %bb.2(0x80000000)90 91 bb.2:92 successors: %bb.1(0x04000000), %bb.2(0x7c000000)93 94 CBZX %1, %bb.195 B %bb.296 97...98---99name: removeUxtw100tracksRegLiveness: true101body: |102 bb.0.entry:103 liveins: $x0104 ; CHECK-LABEL: name: removeUxtw105 ; CHECK: liveins: $x0106 ; CHECK-NEXT: {{ $}}107 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0108 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32109 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32110 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY2]], 1, 0111 ; CHECK-NEXT: $w0 = COPY [[ADDWri]]112 ; CHECK-NEXT: RET_ReallyLR implicit $w0113 %0:gpr64 = COPY $x0114 %1:gpr32 = COPY %0.sub_32115 %2:gpr32 = ORRWrr $wzr, %1116 %3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32117 %4:gpr32sp = COPY %3.sub_32118 %5:gpr32sp = ADDWri %4, 1, 0119 $w0 = COPY %5120 RET_ReallyLR implicit $w0121...122---123name: extraUseOrr124tracksRegLiveness: true125body: |126 bb.0.entry:127 liveins: $x0128 ; CHECK-LABEL: name: extraUseOrr129 ; CHECK: liveins: $x0130 ; CHECK-NEXT: {{ $}}131 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0132 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32133 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr $wzr, [[COPY1]]134 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrr]], %subreg.sub_32135 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32136 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY2]], 1, 0137 ; CHECK-NEXT: $w0 = COPY [[ADDWri]]138 ; CHECK-NEXT: $w1 = COPY [[ORRWrr]]139 ; CHECK-NEXT: RET_ReallyLR implicit $w0140 %0:gpr64 = COPY $x0141 %1:gpr32 = COPY %0.sub_32142 %2:gpr32 = ORRWrr $wzr, %1143 %3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32144 %4:gpr32sp = COPY %3.sub_32145 %5:gpr32sp = ADDWri %4, 1, 0146 $w0 = COPY %5147 $w1 = COPY %2148 RET_ReallyLR implicit $w0149...150