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1; RUN: llc < %s -O3 -mtriple=aarch64 -mcpu=cortex-a53 | FileCheck %s2 3; With cortex-a53, each of fmul and fcvt have latency of 6 cycles. After the4; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive. The top-down5; post-RA MI scheduler will clean this up.6 7@d1 = common global double 0.000000e+00, align 88 9define i32 @test1(float %s2, float %s3, double %d, i32 %i2, i32 %i3) {10entry:11; CHECK-LABEL: @test112; CHECK: fmul13; CHECK-NEXT: add14; CHECK: fcvt15; CHECK-NEXT: mul16 %mul = fmul float %s2, %s317 %conv = fpext float %mul to double18 %div = fdiv double %d, %conv19 store double %div, ptr @d1, align 820 %factor = shl i32 %i3, 121 %add1 = add i32 %i2, 422 %add2 = add i32 %add1, %factor23 %add3 = add nsw i32 %add2, %i224 %add4 = add nsw i32 %add3, %add225 %mul5 = mul i32 %add3, %add326 %mul6 = mul i32 %mul5, %add427 %mul7 = shl i32 %add4, 128 %factor18 = mul i32 %mul7, %mul629 %add9 = add i32 %factor18, %mul630 ret i32 %add931}32