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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- -aarch64-enable-sink-fold=true | FileCheck %s3 4declare float @llvm.pow.f32(float, float)5declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)6 7declare double @llvm.pow.f64(double, double)8declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)9 10define float @pow_f32_one_fourth_fmf(float %x) nounwind {11; CHECK-LABEL: pow_f32_one_fourth_fmf:12; CHECK: // %bb.0:13; CHECK-NEXT: fsqrt s0, s014; CHECK-NEXT: fsqrt s0, s015; CHECK-NEXT: ret16 %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)17 ret float %r18}19 20define double @pow_f64_one_fourth_fmf(double %x) nounwind {21; CHECK-LABEL: pow_f64_one_fourth_fmf:22; CHECK: // %bb.0:23; CHECK-NEXT: fsqrt d0, d024; CHECK-NEXT: fsqrt d0, d025; CHECK-NEXT: ret26 %r = call nsz ninf afn double @llvm.pow.f64(double %x, double 2.5e-01)27 ret double %r28}29 30define <4 x float> @pow_v4f32_one_fourth_fmf(<4 x float> %x) nounwind {31; CHECK-LABEL: pow_v4f32_one_fourth_fmf:32; CHECK: // %bb.0:33; CHECK-NEXT: fsqrt v0.4s, v0.4s34; CHECK-NEXT: fsqrt v0.4s, v0.4s35; CHECK-NEXT: ret36 %r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)37 ret <4 x float> %r38}39 40define <2 x double> @pow_v2f64_one_fourth_fmf(<2 x double> %x) nounwind {41; CHECK-LABEL: pow_v2f64_one_fourth_fmf:42; CHECK: // %bb.0:43; CHECK-NEXT: fsqrt v0.2d, v0.2d44; CHECK-NEXT: fsqrt v0.2d, v0.2d45; CHECK-NEXT: ret46 %r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>)47 ret <2 x double> %r48}49 50define float @pow_f32_one_fourth_not_enough_fmf(float %x) nounwind {51; CHECK-LABEL: pow_f32_one_fourth_not_enough_fmf:52; CHECK: // %bb.0:53; CHECK-NEXT: fmov s1, #0.2500000054; CHECK-NEXT: b powf55 %r = call afn ninf float @llvm.pow.f32(float %x, float 2.5e-01)56 ret float %r57}58 59define double @pow_f64_one_fourth_not_enough_fmf(double %x) nounwind {60; CHECK-LABEL: pow_f64_one_fourth_not_enough_fmf:61; CHECK: // %bb.0:62; CHECK-NEXT: fmov d1, #0.2500000063; CHECK-NEXT: b pow64 %r = call nsz ninf double @llvm.pow.f64(double %x, double 2.5e-01)65 ret double %r66}67 68define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind {69; CHECK-LABEL: pow_v4f32_one_fourth_not_enough_fmf:70; CHECK: // %bb.0:71; CHECK-NEXT: sub sp, sp, #4872; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill73; CHECK-NEXT: mov s0, v0.s[1]74; CHECK-NEXT: fmov s1, #0.2500000075; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill76; CHECK-NEXT: bl powf77; CHECK-NEXT: fmov s1, #0.2500000078; CHECK-NEXT: // kill: def $s0 killed $s0 def $q079; CHECK-NEXT: str q0, [sp] // 16-byte Spill80; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload81; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q082; CHECK-NEXT: bl powf83; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload84; CHECK-NEXT: // kill: def $s0 killed $s0 def $q085; CHECK-NEXT: mov v0.s[1], v1.s[0]86; CHECK-NEXT: fmov s1, #0.2500000087; CHECK-NEXT: str q0, [sp] // 16-byte Spill88; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload89; CHECK-NEXT: mov s0, v0.s[2]90; CHECK-NEXT: bl powf91; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload92; CHECK-NEXT: // kill: def $s0 killed $s0 def $q093; CHECK-NEXT: mov v1.s[2], v0.s[0]94; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Reload95; CHECK-NEXT: mov s0, v0.s[3]96; CHECK-NEXT: str q1, [sp] // 16-byte Spill97; CHECK-NEXT: fmov s1, #0.2500000098; CHECK-NEXT: bl powf99; CHECK-NEXT: ldr q1, [sp] // 16-byte Reload100; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0101; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload102; CHECK-NEXT: mov v1.s[3], v0.s[0]103; CHECK-NEXT: mov v0.16b, v1.16b104; CHECK-NEXT: add sp, sp, #48105; CHECK-NEXT: ret106 %r = call afn nsz <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)107 ret <4 x float> %r108}109 110define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwind {111; CHECK-LABEL: pow_v2f64_one_fourth_not_enough_fmf:112; CHECK: // %bb.0:113; CHECK-NEXT: sub sp, sp, #48114; CHECK-NEXT: str q0, [sp] // 16-byte Spill115; CHECK-NEXT: mov d0, v0.d[1]116; CHECK-NEXT: fmov d1, #0.25000000117; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill118; CHECK-NEXT: bl pow119; CHECK-NEXT: fmov d1, #0.25000000120; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0121; CHECK-NEXT: str q0, [sp, #16] // 16-byte Spill122; CHECK-NEXT: ldr q0, [sp] // 16-byte Reload123; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0124; CHECK-NEXT: bl pow125; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Reload126; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0127; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload128; CHECK-NEXT: mov v0.d[1], v1.d[0]129; CHECK-NEXT: add sp, sp, #48130; CHECK-NEXT: ret131 %r = call nsz nnan reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>)132 ret <2 x double> %r133}134 135