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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s3 4define <vscale x 4 x i8> @widget(i1 %arg, <vscale x 4 x i1> %arg1, <vscale x 4 x i8> %arg2, <vscale x 4 x i8> %arg3) {5; CHECK-LABEL: widget:6; CHECK: // %bb.0: // %bb7; CHECK-NEXT: mvn w8, w08; CHECK-NEXT: sbfx x8, x8, #0, #19; CHECK-NEXT: whilelo p1.s, xzr, x810; CHECK-NEXT: mov z1.s, p1/z, #1 // =0x111; CHECK-NEXT: orr z0.d, z1.d, z0.d12; CHECK-NEXT: mov z0.s, p0/m, z1.s13; CHECK-NEXT: ret14bb:15 %insertelement = insertelement <vscale x 4 x i1> zeroinitializer, i1 %arg, i64 016 %shufflevector = shufflevector <vscale x 4 x i1> %insertelement, <vscale x 4 x i1> zeroinitializer, <vscale x 4 x i32> zeroinitializer17 %xor = xor <vscale x 4 x i1> %shufflevector, splat (i1 true)18 %zext = zext <vscale x 4 x i1> %xor to <vscale x 4 x i8>19 %select = select <vscale x 4 x i1> %arg1, <vscale x 4 x i8> zeroinitializer, <vscale x 4 x i8> %arg220 %or = or <vscale x 4 x i8> %select, %zext21 ret <vscale x 4 x i8> %or22}23