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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s3 4; This used to hit an assertion caused by dagcombine merge store.5; When the store memVT is v1f32 and the other store to be merged6; is f32, we need to build vector for the f32 store.7 8define void @f(<1 x float> %a, i64 %b) {9; CHECK-LABEL: f:10; CHECK: // %bb.0:11; CHECK-NEXT: sub sp, sp, #1612; CHECK-NEXT: .cfi_def_cfa_offset 1613; CHECK-NEXT: adrp x8, .LCPI0_014; CHECK-NEXT: mov x9, sp15; CHECK-NEXT: // kill: def $d0 killed $d0 def $q016; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]17; CHECK-NEXT: bfi x9, x0, #2, #118; CHECK-NEXT: str d1, [sp]19; CHECK-NEXT: ldr s1, [x9]20; CHECK-NEXT: mov v1.s[1], v0.s[0]21; CHECK-NEXT: str d1, [sp, #8]22; CHECK-NEXT: add sp, sp, #1623; CHECK-NEXT: ret24 %P = alloca i6425 %E = extractelement <2 x float> <float 0.5, float 1.0>, i64 %b26 %G = getelementptr <1 x float>, ptr %P, i64 127 store float %E, ptr %P28 store <1 x float> %a, ptr %G29 ret void30}31