451 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux"5 6define <vscale x 8 x i8> @zext.add.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {7; CHECK-LABEL: zext.add.8xi8:8; CHECK: // %bb.0:9; CHECK-NEXT: mov z1.h, #1 // =0x110; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h11; CHECK-NEXT: ret12 %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>13 %result = add <vscale x 8 x i8> %a, %extend14 ret <vscale x 8 x i8> %result15}16 17define <vscale x 4 x i16> @zext.add.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {18; CHECK-LABEL: zext.add.4xi16:19; CHECK: // %bb.0:20; CHECK-NEXT: mov z1.s, #1 // =0x121; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s22; CHECK-NEXT: ret23 %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>24 %result = add <vscale x 4 x i16> %a, %extend25 ret <vscale x 4 x i16> %result26}27 28define <vscale x 2 x i32> @zext.add.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {29; CHECK-LABEL: zext.add.2xi32:30; CHECK: // %bb.0:31; CHECK-NEXT: mov z1.d, #1 // =0x132; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d33; CHECK-NEXT: ret34 %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>35 %result = add <vscale x 2 x i32> %a, %extend36 ret <vscale x 2 x i32> %result37}38 39define <vscale x 16 x i8> @zext.add.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {40; CHECK-LABEL: zext.add.16xi8:41; CHECK: // %bb.0:42; CHECK-NEXT: mov z1.b, #1 // =0x143; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b44; CHECK-NEXT: ret45 %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>46 %result = add <vscale x 16 x i8> %a, %extend47 ret <vscale x 16 x i8> %result48}49 50define <vscale x 8 x i16> @zext.add.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {51; CHECK-LABEL: zext.add.8xi16:52; CHECK: // %bb.0:53; CHECK-NEXT: mov z1.h, #1 // =0x154; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h55; CHECK-NEXT: ret56 %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>57 %result = add <vscale x 8 x i16> %a, %extend58 ret <vscale x 8 x i16> %result59}60 61define <vscale x 4 x i32> @zext.add.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {62; CHECK-LABEL: zext.add.4xi32:63; CHECK: // %bb.0:64; CHECK-NEXT: mov z1.s, #1 // =0x165; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s66; CHECK-NEXT: ret67 %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>68 %result = add <vscale x 4 x i32> %a, %extend69 ret <vscale x 4 x i32> %result70}71 72define <vscale x 2 x i64> @zext.add.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {73; CHECK-LABEL: zext.add.2xi64:74; CHECK: // %bb.0:75; CHECK-NEXT: mov z1.d, #1 // =0x176; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d77; CHECK-NEXT: ret78 %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>79 %result = add <vscale x 2 x i64> %a, %extend80 ret <vscale x 2 x i64> %result81}82 83define <vscale x 8 x i32> @zext.add.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {84; CHECK-LABEL: zext.add.8xi32:85; CHECK: // %bb.0:86; CHECK-NEXT: mov z2.s, #1 // =0x187; CHECK-NEXT: punpkhi p1.h, p0.b88; CHECK-NEXT: punpklo p0.h, p0.b89; CHECK-NEXT: add z0.s, p0/m, z0.s, z2.s90; CHECK-NEXT: add z1.s, p1/m, z1.s, z2.s91; CHECK-NEXT: ret92 %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>93 %result = add <vscale x 8 x i32> %a, %extend94 ret <vscale x 8 x i32> %result95}96 97define <vscale x 16 x i32> @zext.add.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {98; CHECK-LABEL: zext.add.16xi32:99; CHECK: // %bb.0:100; CHECK-NEXT: punpkhi p1.h, p0.b101; CHECK-NEXT: mov z4.s, #1 // =0x1102; CHECK-NEXT: punpklo p0.h, p0.b103; CHECK-NEXT: punpkhi p2.h, p1.b104; CHECK-NEXT: punpklo p1.h, p1.b105; CHECK-NEXT: punpklo p3.h, p0.b106; CHECK-NEXT: add z3.s, p2/m, z3.s, z4.s107; CHECK-NEXT: punpkhi p0.h, p0.b108; CHECK-NEXT: add z2.s, p1/m, z2.s, z4.s109; CHECK-NEXT: add z0.s, p3/m, z0.s, z4.s110; CHECK-NEXT: add z1.s, p0/m, z1.s, z4.s111; CHECK-NEXT: ret112 %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>113 %result = add <vscale x 16 x i32> %a, %extend114 ret <vscale x 16 x i32> %result115}116 117define <vscale x 8 x i8> @zext.sub.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {118; CHECK-LABEL: zext.sub.8xi8:119; CHECK: // %bb.0:120; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff121; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h122; CHECK-NEXT: ret123 %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>124 %result = sub <vscale x 8 x i8> %a, %extend125 ret <vscale x 8 x i8> %result126}127 128define <vscale x 4 x i16> @zext.sub.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {129; CHECK-LABEL: zext.sub.4xi16:130; CHECK: // %bb.0:131; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff132; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s133; CHECK-NEXT: ret134 %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i16>135 %result = sub <vscale x 4 x i16> %a, %extend136 ret <vscale x 4 x i16> %result137}138 139define <vscale x 2 x i32> @zext.sub.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {140; CHECK-LABEL: zext.sub.2xi32:141; CHECK: // %bb.0:142; CHECK-NEXT: mov z1.d, #-1 // =0xffffffffffffffff143; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d144; CHECK-NEXT: ret145 %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i32>146 %result = sub <vscale x 2 x i32> %a, %extend147 ret <vscale x 2 x i32> %result148}149 150define <vscale x 16 x i8> @zext.sub.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {151; CHECK-LABEL: zext.sub.16xi8:152; CHECK: // %bb.0:153; CHECK-NEXT: mov z1.b, #-1 // =0xffffffffffffffff154; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b155; CHECK-NEXT: ret156 %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>157 %result = sub <vscale x 16 x i8> %a, %extend158 ret <vscale x 16 x i8> %result159}160 161define <vscale x 8 x i16> @zext.sub.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {162; CHECK-LABEL: zext.sub.8xi16:163; CHECK: // %bb.0:164; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff165; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h166; CHECK-NEXT: ret167 %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i16>168 %result = sub <vscale x 8 x i16> %a, %extend169 ret <vscale x 8 x i16> %result170}171 172define <vscale x 4 x i32> @zext.sub.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {173; CHECK-LABEL: zext.sub.4xi32:174; CHECK: // %bb.0:175; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff176; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s177; CHECK-NEXT: ret178 %extend = zext <vscale x 4 x i1> %v to <vscale x 4 x i32>179 %result = sub <vscale x 4 x i32> %a, %extend180 ret <vscale x 4 x i32> %result181}182 183define <vscale x 2 x i64> @zext.sub.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {184; CHECK-LABEL: zext.sub.2xi64:185; CHECK: // %bb.0:186; CHECK-NEXT: mov z1.d, #-1 // =0xffffffffffffffff187; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d188; CHECK-NEXT: ret189 %extend = zext <vscale x 2 x i1> %v to <vscale x 2 x i64>190 %result = sub <vscale x 2 x i64> %a, %extend191 ret <vscale x 2 x i64> %result192}193 194define <vscale x 8 x i32> @zext.sub.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {195; CHECK-LABEL: zext.sub.8xi32:196; CHECK: // %bb.0:197; CHECK-NEXT: mov z2.s, #-1 // =0xffffffffffffffff198; CHECK-NEXT: punpklo p1.h, p0.b199; CHECK-NEXT: punpkhi p0.h, p0.b200; CHECK-NEXT: add z0.s, p1/m, z0.s, z2.s201; CHECK-NEXT: add z1.s, p0/m, z1.s, z2.s202; CHECK-NEXT: ret203 %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i32>204 %result = sub <vscale x 8 x i32> %a, %extend205 ret <vscale x 8 x i32> %result206}207 208define <vscale x 16 x i32> @zext.sub.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {209; CHECK-LABEL: zext.sub.16xi32:210; CHECK: // %bb.0:211; CHECK-NEXT: punpklo p1.h, p0.b212; CHECK-NEXT: mov z4.s, #-1 // =0xffffffffffffffff213; CHECK-NEXT: punpkhi p0.h, p0.b214; CHECK-NEXT: punpklo p2.h, p1.b215; CHECK-NEXT: punpkhi p1.h, p1.b216; CHECK-NEXT: punpklo p3.h, p0.b217; CHECK-NEXT: add z0.s, p2/m, z0.s, z4.s218; CHECK-NEXT: punpkhi p0.h, p0.b219; CHECK-NEXT: add z1.s, p1/m, z1.s, z4.s220; CHECK-NEXT: add z2.s, p3/m, z2.s, z4.s221; CHECK-NEXT: add z3.s, p0/m, z3.s, z4.s222; CHECK-NEXT: ret223 %extend = zext <vscale x 16 x i1> %v to <vscale x 16 x i32>224 %result = sub <vscale x 16 x i32> %a, %extend225 ret <vscale x 16 x i32> %result226}227 228define <vscale x 8 x i8> @sext.add.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {229; CHECK-LABEL: sext.add.8xi8:230; CHECK: // %bb.0:231; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff232; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h233; CHECK-NEXT: ret234 %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>235 %result = add <vscale x 8 x i8> %a, %extend236 ret <vscale x 8 x i8> %result237}238 239define <vscale x 4 x i16> @sext.add.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {240; CHECK-LABEL: sext.add.4xi16:241; CHECK: // %bb.0:242; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff243; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s244; CHECK-NEXT: ret245 %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>246 %result = add <vscale x 4 x i16> %a, %extend247 ret <vscale x 4 x i16> %result248}249 250define <vscale x 2 x i32> @sext.add.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {251; CHECK-LABEL: sext.add.2xi32:252; CHECK: // %bb.0:253; CHECK-NEXT: mov z1.d, #-1 // =0xffffffffffffffff254; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d255; CHECK-NEXT: ret256 %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>257 %result = add <vscale x 2 x i32> %a, %extend258 ret <vscale x 2 x i32> %result259}260 261define <vscale x 16 x i8> @sext.add.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {262; CHECK-LABEL: sext.add.16xi8:263; CHECK: // %bb.0:264; CHECK-NEXT: mov z1.b, #-1 // =0xffffffffffffffff265; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b266; CHECK-NEXT: ret267 %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>268 %result = add <vscale x 16 x i8> %a, %extend269 ret <vscale x 16 x i8> %result270}271 272define <vscale x 8 x i16> @sext.add.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {273; CHECK-LABEL: sext.add.8xi16:274; CHECK: // %bb.0:275; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff276; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h277; CHECK-NEXT: ret278 %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>279 %result = add <vscale x 8 x i16> %a, %extend280 ret <vscale x 8 x i16> %result281}282 283define <vscale x 4 x i32> @sext.add.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {284; CHECK-LABEL: sext.add.4xi32:285; CHECK: // %bb.0:286; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff287; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s288; CHECK-NEXT: ret289 %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>290 %result = add <vscale x 4 x i32> %a, %extend291 ret <vscale x 4 x i32> %result292}293 294define <vscale x 2 x i64> @sext.add.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {295; CHECK-LABEL: sext.add.2xi64:296; CHECK: // %bb.0:297; CHECK-NEXT: mov z1.d, #-1 // =0xffffffffffffffff298; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d299; CHECK-NEXT: ret300 %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>301 %result = add <vscale x 2 x i64> %a, %extend302 ret <vscale x 2 x i64> %result303}304 305define <vscale x 8 x i32> @sext.add.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {306; CHECK-LABEL: sext.add.8xi32:307; CHECK: // %bb.0:308; CHECK-NEXT: mov z2.s, #-1 // =0xffffffffffffffff309; CHECK-NEXT: punpkhi p1.h, p0.b310; CHECK-NEXT: punpklo p0.h, p0.b311; CHECK-NEXT: add z0.s, p0/m, z0.s, z2.s312; CHECK-NEXT: add z1.s, p1/m, z1.s, z2.s313; CHECK-NEXT: ret314 %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>315 %result = add <vscale x 8 x i32> %a, %extend316 ret <vscale x 8 x i32> %result317}318 319define <vscale x 16 x i32> @sext.add.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {320; CHECK-LABEL: sext.add.16xi32:321; CHECK: // %bb.0:322; CHECK-NEXT: punpkhi p1.h, p0.b323; CHECK-NEXT: mov z4.s, #-1 // =0xffffffffffffffff324; CHECK-NEXT: punpklo p0.h, p0.b325; CHECK-NEXT: punpkhi p2.h, p1.b326; CHECK-NEXT: punpklo p1.h, p1.b327; CHECK-NEXT: punpklo p3.h, p0.b328; CHECK-NEXT: add z3.s, p2/m, z3.s, z4.s329; CHECK-NEXT: punpkhi p0.h, p0.b330; CHECK-NEXT: add z2.s, p1/m, z2.s, z4.s331; CHECK-NEXT: add z0.s, p3/m, z0.s, z4.s332; CHECK-NEXT: add z1.s, p0/m, z1.s, z4.s333; CHECK-NEXT: ret334 %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>335 %result = add <vscale x 16 x i32> %a, %extend336 ret <vscale x 16 x i32> %result337}338 339define <vscale x 8 x i8> @sext.sub.8xi8(<vscale x 8 x i8> %a, <vscale x 8 x i1> %v) #0 {340; CHECK-LABEL: sext.sub.8xi8:341; CHECK: // %bb.0:342; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff343; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h344; CHECK-NEXT: ret345 %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i8>346 %result = sub <vscale x 8 x i8> %a, %extend347 ret <vscale x 8 x i8> %result348}349 350define <vscale x 4 x i16> @sext.sub.4xi16(<vscale x 4 x i16> %a, <vscale x 4 x i1> %v) #0 {351; CHECK-LABEL: sext.sub.4xi16:352; CHECK: // %bb.0:353; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff354; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s355; CHECK-NEXT: ret356 %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i16>357 %result = sub <vscale x 4 x i16> %a, %extend358 ret <vscale x 4 x i16> %result359}360 361define <vscale x 2 x i32> @sext.sub.2xi32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %v) #0 {362; CHECK-LABEL: sext.sub.2xi32:363; CHECK: // %bb.0:364; CHECK-NEXT: mov z1.d, #-1 // =0xffffffffffffffff365; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d366; CHECK-NEXT: ret367 %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i32>368 %result = sub <vscale x 2 x i32> %a, %extend369 ret <vscale x 2 x i32> %result370}371 372define <vscale x 16 x i8> @sext.sub.16xi8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %v) #0 {373; CHECK-LABEL: sext.sub.16xi8:374; CHECK: // %bb.0:375; CHECK-NEXT: mov z1.b, #-1 // =0xffffffffffffffff376; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b377; CHECK-NEXT: ret378 %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i8>379 %result = sub <vscale x 16 x i8> %a, %extend380 ret <vscale x 16 x i8> %result381}382 383define <vscale x 8 x i16> @sext.sub.8xi16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %v) #0 {384; CHECK-LABEL: sext.sub.8xi16:385; CHECK: // %bb.0:386; CHECK-NEXT: mov z1.h, #-1 // =0xffffffffffffffff387; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h388; CHECK-NEXT: ret389 %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i16>390 %result = sub <vscale x 8 x i16> %a, %extend391 ret <vscale x 8 x i16> %result392}393 394define <vscale x 4 x i32> @sext.sub.4xi32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %v) #0 {395; CHECK-LABEL: sext.sub.4xi32:396; CHECK: // %bb.0:397; CHECK-NEXT: mov z1.s, #-1 // =0xffffffffffffffff398; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s399; CHECK-NEXT: ret400 %extend = sext <vscale x 4 x i1> %v to <vscale x 4 x i32>401 %result = sub <vscale x 4 x i32> %a, %extend402 ret <vscale x 4 x i32> %result403}404 405define <vscale x 2 x i64> @sext.sub.2xi64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %v) #0 {406; CHECK-LABEL: sext.sub.2xi64:407; CHECK: // %bb.0:408; CHECK-NEXT: mov z1.d, #-1 // =0xffffffffffffffff409; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d410; CHECK-NEXT: ret411 %extend = sext <vscale x 2 x i1> %v to <vscale x 2 x i64>412 %result = sub <vscale x 2 x i64> %a, %extend413 ret <vscale x 2 x i64> %result414}415 416define <vscale x 8 x i32> @sext.sub.8xi32(<vscale x 8 x i32> %a, <vscale x 8 x i1> %v) #0 {417; CHECK-LABEL: sext.sub.8xi32:418; CHECK: // %bb.0:419; CHECK-NEXT: mov z2.s, #-1 // =0xffffffffffffffff420; CHECK-NEXT: punpkhi p1.h, p0.b421; CHECK-NEXT: punpklo p0.h, p0.b422; CHECK-NEXT: sub z0.s, p0/m, z0.s, z2.s423; CHECK-NEXT: sub z1.s, p1/m, z1.s, z2.s424; CHECK-NEXT: ret425 %extend = sext <vscale x 8 x i1> %v to <vscale x 8 x i32>426 %result = sub <vscale x 8 x i32> %a, %extend427 ret <vscale x 8 x i32> %result428}429 430define <vscale x 16 x i32> @sext.sub.16xi32(<vscale x 16 x i32> %a, <vscale x 16 x i1> %v) #0 {431; CHECK-LABEL: sext.sub.16xi32:432; CHECK: // %bb.0:433; CHECK-NEXT: punpkhi p1.h, p0.b434; CHECK-NEXT: mov z4.s, #-1 // =0xffffffffffffffff435; CHECK-NEXT: punpklo p0.h, p0.b436; CHECK-NEXT: punpkhi p2.h, p1.b437; CHECK-NEXT: punpklo p1.h, p1.b438; CHECK-NEXT: punpklo p3.h, p0.b439; CHECK-NEXT: sub z3.s, p2/m, z3.s, z4.s440; CHECK-NEXT: punpkhi p0.h, p0.b441; CHECK-NEXT: sub z2.s, p1/m, z2.s, z4.s442; CHECK-NEXT: sub z0.s, p3/m, z0.s, z4.s443; CHECK-NEXT: sub z1.s, p0/m, z1.s, z4.s444; CHECK-NEXT: ret445 %extend = sext <vscale x 16 x i1> %v to <vscale x 16 x i32>446 %result = sub <vscale x 16 x i32> %a, %extend447 ret <vscale x 16 x i32> %result448}449 450attributes #0 = { "target-features"="+sve" }451