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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc %s -mtriple=aarch64 -o - | FileCheck %s3 4define <4 x i16> @NarrowAShrI32By5(<4 x i32> %x) {5; CHECK-LABEL: NarrowAShrI32By5:6; CHECK: // %bb.0:7; CHECK-NEXT: sqshrn v0.4h, v0.4s, #58; CHECK-NEXT: ret9 %s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>10 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)11 ret <4 x i16> %r12}13 14define <4 x i16> @NarrowAShrU32By5(<4 x i32> %x) {15; CHECK-LABEL: NarrowAShrU32By5:16; CHECK: // %bb.0:17; CHECK-NEXT: sshr v0.4s, v0.4s, #518; CHECK-NEXT: uqxtn v0.4h, v0.4s19; CHECK-NEXT: ret20 %s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>21 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)22 ret <4 x i16> %r23}24 25define <4 x i16> @NarrowAShrI32By5ToU16(<4 x i32> %x) {26; CHECK-LABEL: NarrowAShrI32By5ToU16:27; CHECK: // %bb.0:28; CHECK-NEXT: sqshrun v0.4h, v0.4s, #529; CHECK-NEXT: ret30 %s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>31 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)32 ret <4 x i16> %r33}34 35define <4 x i16> @NarrowLShrI32By5(<4 x i32> %x) {36; CHECK-LABEL: NarrowLShrI32By5:37; CHECK: // %bb.0:38; CHECK-NEXT: ushr v0.4s, v0.4s, #539; CHECK-NEXT: sqxtn v0.4h, v0.4s40; CHECK-NEXT: ret41 %s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>42 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)43 ret <4 x i16> %r44}45 46define <4 x i16> @NarrowLShrU32By5(<4 x i32> %x) {47; CHECK-LABEL: NarrowLShrU32By5:48; CHECK: // %bb.0:49; CHECK-NEXT: uqshrn v0.4h, v0.4s, #550; CHECK-NEXT: ret51 %s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>52 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)53 ret <4 x i16> %r54}55 56define <4 x i16> @NarrowLShrI32By5ToU16(<4 x i32> %x) {57; CHECK-LABEL: NarrowLShrI32By5ToU16:58; CHECK: // %bb.0:59; CHECK-NEXT: ushr v0.4s, v0.4s, #560; CHECK-NEXT: sqxtun v0.4h, v0.4s61; CHECK-NEXT: ret62 %s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>63 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)64 ret <4 x i16> %r65}66 67 68define <2 x i32> @NarrowAShri64By5(<2 x i64> %x) {69; CHECK-LABEL: NarrowAShri64By5:70; CHECK: // %bb.0:71; CHECK-NEXT: sqshrn v0.2s, v0.2d, #572; CHECK-NEXT: ret73 %s = ashr <2 x i64> %x, <i64 5, i64 5>74 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %s)75 ret <2 x i32> %r76}77 78define <2 x i32> @NarrowAShrU64By5(<2 x i64> %x) {79; CHECK-LABEL: NarrowAShrU64By5:80; CHECK: // %bb.0:81; CHECK-NEXT: sshr v0.2d, v0.2d, #582; CHECK-NEXT: uqxtn v0.2s, v0.2d83; CHECK-NEXT: ret84 %s = ashr <2 x i64> %x, <i64 5, i64 5>85 %r = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %s)86 ret <2 x i32> %r87}88 89define <2 x i32> @NarrowAShri64By5ToU32(<2 x i64> %x) {90; CHECK-LABEL: NarrowAShri64By5ToU32:91; CHECK: // %bb.0:92; CHECK-NEXT: sqshrun v0.2s, v0.2d, #593; CHECK-NEXT: ret94 %s = ashr <2 x i64> %x, <i64 5, i64 5>95 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %s)96 ret <2 x i32> %r97}98 99define <2 x i32> @NarrowLShri64By5(<2 x i64> %x) {100; CHECK-LABEL: NarrowLShri64By5:101; CHECK: // %bb.0:102; CHECK-NEXT: ushr v0.2d, v0.2d, #5103; CHECK-NEXT: sqxtn v0.2s, v0.2d104; CHECK-NEXT: ret105 %s = lshr <2 x i64> %x, <i64 5, i64 5>106 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %s)107 ret <2 x i32> %r108}109 110define <2 x i32> @NarrowLShrU64By5(<2 x i64> %x) {111; CHECK-LABEL: NarrowLShrU64By5:112; CHECK: // %bb.0:113; CHECK-NEXT: uqshrn v0.2s, v0.2d, #5114; CHECK-NEXT: ret115 %s = lshr <2 x i64> %x, <i64 5, i64 5>116 %r = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %s)117 ret <2 x i32> %r118}119 120define <2 x i32> @NarrowLShri64By5ToU32(<2 x i64> %x) {121; CHECK-LABEL: NarrowLShri64By5ToU32:122; CHECK: // %bb.0:123; CHECK-NEXT: ushr v0.2d, v0.2d, #5124; CHECK-NEXT: sqxtun v0.2s, v0.2d125; CHECK-NEXT: ret126 %s = lshr <2 x i64> %x, <i64 5, i64 5>127 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %s)128 ret <2 x i32> %r129}130 131 132define <8 x i8> @NarrowAShri16By5(<8 x i16> %x) {133; CHECK-LABEL: NarrowAShri16By5:134; CHECK: // %bb.0:135; CHECK-NEXT: sqshrn v0.8b, v0.8h, #5136; CHECK-NEXT: ret137 %s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>138 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %s)139 ret <8 x i8> %r140}141 142define <8 x i8> @NarrowAShrU16By5(<8 x i16> %x) {143; CHECK-LABEL: NarrowAShrU16By5:144; CHECK: // %bb.0:145; CHECK-NEXT: sshr v0.8h, v0.8h, #5146; CHECK-NEXT: uqxtn v0.8b, v0.8h147; CHECK-NEXT: ret148 %s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>149 %r = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %s)150 ret <8 x i8> %r151}152 153define <8 x i8> @NarrowAShri16By5ToU8(<8 x i16> %x) {154; CHECK-LABEL: NarrowAShri16By5ToU8:155; CHECK: // %bb.0:156; CHECK-NEXT: sqshrun v0.8b, v0.8h, #5157; CHECK-NEXT: ret158 %s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>159 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %s)160 ret <8 x i8> %r161}162 163define <8 x i8> @NarrowLShri16By5(<8 x i16> %x) {164; CHECK-LABEL: NarrowLShri16By5:165; CHECK: // %bb.0:166; CHECK-NEXT: ushr v0.8h, v0.8h, #5167; CHECK-NEXT: sqxtn v0.8b, v0.8h168; CHECK-NEXT: ret169 %s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>170 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %s)171 ret <8 x i8> %r172}173 174define <8 x i8> @NarrowLShrU16By5(<8 x i16> %x) {175; CHECK-LABEL: NarrowLShrU16By5:176; CHECK: // %bb.0:177; CHECK-NEXT: uqshrn v0.8b, v0.8h, #5178; CHECK-NEXT: ret179 %s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>180 %r = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %s)181 ret <8 x i8> %r182}183 184define <8 x i8> @NarrowLShri16By5ToU8(<8 x i16> %x) {185; CHECK-LABEL: NarrowLShri16By5ToU8:186; CHECK: // %bb.0:187; CHECK-NEXT: ushr v0.8h, v0.8h, #5188; CHECK-NEXT: sqxtun v0.8b, v0.8h189; CHECK-NEXT: ret190 %s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>191 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %s)192 ret <8 x i8> %r193}194 195 196 197 198 199define <4 x i16> @NarrowAShrI32By31(<4 x i32> %x) {200; CHECK-LABEL: NarrowAShrI32By31:201; CHECK: // %bb.0:202; CHECK-NEXT: sqshrn v0.4h, v0.4s, #16203; CHECK-NEXT: ret204 %s = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>205 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)206 ret <4 x i16> %r207}208 209define <4 x i16> @NarrowAShrI32By31ToU16(<4 x i32> %x) {210; CHECK-LABEL: NarrowAShrI32By31ToU16:211; CHECK: // %bb.0:212; CHECK-NEXT: sqshrun v0.4h, v0.4s, #16213; CHECK-NEXT: ret214 %s = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>215 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)216 ret <4 x i16> %r217}218 219define <4 x i16> @NarrowLShrU32By31(<4 x i32> %x) {220; CHECK-LABEL: NarrowLShrU32By31:221; CHECK: // %bb.0:222; CHECK-NEXT: uqshrn v0.4h, v0.4s, #16223; CHECK-NEXT: ret224 %s = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>225 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)226 ret <4 x i16> %r227}228 229 230define <16 x i8> @signed_minmax_v8i16_to_v16i8(<16 x i16> %x) {231; CHECK-LABEL: signed_minmax_v8i16_to_v16i8:232; CHECK: // %bb.0: // %entry233; CHECK-NEXT: sqshrn v0.8b, v0.8h, #5234; CHECK-NEXT: sqshrn2 v0.16b, v1.8h, #5235; CHECK-NEXT: ret236entry:237 %s = ashr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>238 %min = call <16 x i16> @llvm.smin.v8i16(<16 x i16> %s, <16 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)239 %max = call <16 x i16> @llvm.smax.v8i16(<16 x i16> %min, <16 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)240 %trunc = trunc <16 x i16> %max to <16 x i8>241 ret <16 x i8> %trunc242}243 244define <16 x i8> @unsigned_minmax_v8i16_to_v16i8(<16 x i16> %x) {245; CHECK-LABEL: unsigned_minmax_v8i16_to_v16i8:246; CHECK: // %bb.0: // %entry247; CHECK-NEXT: uqshrn v0.8b, v0.8h, #5248; CHECK-NEXT: uqshrn2 v0.16b, v1.8h, #5249; CHECK-NEXT: ret250entry:251 %s = lshr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>252 %min = call <16 x i16> @llvm.umin.v8i16(<16 x i16> %s, <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)253 %trunc = trunc <16 x i16> %min to <16 x i8>254 ret <16 x i8> %trunc255}256 257define <16 x i8> @unsigned_signed_minmax_v8i16_to_v16i8(<16 x i16> %x) {258; CHECK-LABEL: unsigned_signed_minmax_v8i16_to_v16i8:259; CHECK: // %bb.0: // %entry260; CHECK-NEXT: sqshrun v0.8b, v0.8h, #5261; CHECK-NEXT: sqshrun2 v0.16b, v1.8h, #5262; CHECK-NEXT: ret263entry:264 %s = ashr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>265 %max = call <16 x i16> @llvm.smax.v8i16(<16 x i16> %s, <16 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)266 %min = call <16 x i16> @llvm.umin.v8i16(<16 x i16> %max, <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)267 %trunc = trunc <16 x i16> %min to <16 x i8>268 ret <16 x i8> %trunc269}270 271 272define <8 x i16> @signed_minmax_v4i32_to_v8i16(<8 x i32> %x) {273; CHECK-LABEL: signed_minmax_v4i32_to_v8i16:274; CHECK: // %bb.0: // %entry275; CHECK-NEXT: sqshrn v0.4h, v0.4s, #5276; CHECK-NEXT: sqshrn2 v0.8h, v1.4s, #5277; CHECK-NEXT: ret278entry:279 %s = ashr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>280 %min = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %s, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)281 %max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %min, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)282 %trunc = trunc <8 x i32> %max to <8 x i16>283 ret <8 x i16> %trunc284}285 286define <8 x i16> @unsigned_minmax_v4i32_to_v8i16(<8 x i32> %x) {287; CHECK-LABEL: unsigned_minmax_v4i32_to_v8i16:288; CHECK: // %bb.0: // %entry289; CHECK-NEXT: uqshrn v0.4h, v0.4s, #5290; CHECK-NEXT: uqshrn2 v0.8h, v1.4s, #5291; CHECK-NEXT: ret292entry:293 %s = lshr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>294 %min = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %s, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)295 %trunc = trunc <8 x i32> %min to <8 x i16>296 ret <8 x i16> %trunc297}298 299define <8 x i16> @unsigned_signed_minmax_v4i32_to_v8i16(<8 x i32> %x) {300; CHECK-LABEL: unsigned_signed_minmax_v4i32_to_v8i16:301; CHECK: // %bb.0: // %entry302; CHECK-NEXT: sqshrun v0.4h, v0.4s, #5303; CHECK-NEXT: sqshrun2 v0.8h, v1.4s, #5304; CHECK-NEXT: ret305entry:306 %s = ashr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>307 %max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %s, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>)308 %min = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %max, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)309 %trunc = trunc <8 x i32> %min to <8 x i16>310 ret <8 x i16> %trunc311}312 313 314define <4 x i32> @signed_minmax_v4i64_to_v8i32(<4 x i64> %x) {315; CHECK-LABEL: signed_minmax_v4i64_to_v8i32:316; CHECK: // %bb.0: // %entry317; CHECK-NEXT: sqshrn v0.2s, v0.2d, #5318; CHECK-NEXT: sqshrn2 v0.4s, v1.2d, #5319; CHECK-NEXT: ret320entry:321 %s = ashr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>322 %min = call <4 x i64> @llvm.smin.v8i64(<4 x i64> %s, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)323 %max = call <4 x i64> @llvm.smax.v8i64(<4 x i64> %min, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)324 %trunc = trunc <4 x i64> %max to <4 x i32>325 ret <4 x i32> %trunc326}327 328define <4 x i32> @unsigned_minmax_v4i64_to_v8i32(<4 x i64> %x) {329; CHECK-LABEL: unsigned_minmax_v4i64_to_v8i32:330; CHECK: // %bb.0: // %entry331; CHECK-NEXT: uqshrn v0.2s, v0.2d, #5332; CHECK-NEXT: uqshrn2 v0.4s, v1.2d, #5333; CHECK-NEXT: ret334entry:335 %s = lshr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>336 %min = call <4 x i64> @llvm.umin.v8i64(<4 x i64> %s, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)337 %trunc = trunc <4 x i64> %min to <4 x i32>338 ret <4 x i32> %trunc339}340 341define <4 x i32> @unsigned_signed_minmax_v4i64_to_v8i32(<4 x i64> %x) {342; CHECK-LABEL: unsigned_signed_minmax_v4i64_to_v8i32:343; CHECK: // %bb.0: // %entry344; CHECK-NEXT: sqshrun v0.2s, v0.2d, #5345; CHECK-NEXT: sqshrun2 v0.4s, v1.2d, #5346; CHECK-NEXT: ret347entry:348 %s = ashr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>349 %max = call <4 x i64> @llvm.smax.v8i64(<4 x i64> %s, <4 x i64> <i64 0, i64 0, i64 0, i64 0>)350 %min = call <4 x i64> @llvm.umin.v8i64(<4 x i64> %max, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)351 %trunc = trunc <4 x i64> %min to <4 x i32>352 ret <4 x i32> %trunc353}354