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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand -aarch64-enable-sink-fold=true %s -o - | FileCheck %s3 4define i32 @rndr(ptr %__addr) {5; CHECK-LABEL: rndr:6; CHECK: // %bb.0:7; CHECK-NEXT: mrs x10, RNDR8; CHECK-NEXT: mov x9, x09; CHECK-NEXT: cset w8, eq10; CHECK-NEXT: str x10, [x9]11; CHECK-NEXT: mov w0, w812; CHECK-NEXT: ret13 %1 = tail call { i64, i1 } @llvm.aarch64.rndr()14 %2 = extractvalue { i64, i1 } %1, 015 %3 = extractvalue { i64, i1 } %1, 116 store i64 %2, ptr %__addr, align 817 %4 = zext i1 %3 to i3218 ret i32 %419}20 21 22define i32 @rndrrs(ptr %__addr) {23; CHECK-LABEL: rndrrs:24; CHECK: // %bb.0:25; CHECK-NEXT: mrs x10, RNDRRS26; CHECK-NEXT: mov x9, x027; CHECK-NEXT: cset w8, eq28; CHECK-NEXT: str x10, [x9]29; CHECK-NEXT: mov w0, w830; CHECK-NEXT: ret31 %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()32 %2 = extractvalue { i64, i1 } %1, 033 %3 = extractvalue { i64, i1 } %1, 134 store i64 %2, ptr %__addr, align 835 %4 = zext i1 %3 to i3236 ret i32 %437}38 39declare { i64, i1 } @llvm.aarch64.rndr()40declare { i64, i1 } @llvm.aarch64.rndrrs()41