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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-none-elf -mattr=+sve2 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-elf -mattr=+sve2 -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for smlsl_nxv8i166; CHECK-GI-NEXT: warning: Instruction selection used fallback path for umlsl_nxv8i167; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mls_nxv8i168; CHECK-GI-NEXT: warning: Instruction selection used fallback path for mla_nxv8i169 10define i64 @smlsl_i64(i64 %a, i32 %b, i32 %c, i32 %d, i32 %e) {11; CHECK-SD-LABEL: smlsl_i64:12; CHECK-SD: // %bb.0:13; CHECK-SD-NEXT: smsubl x8, w4, w3, x014; CHECK-SD-NEXT: smsubl x0, w2, w1, x815; CHECK-SD-NEXT: ret16;17; CHECK-GI-LABEL: smlsl_i64:18; CHECK-GI: // %bb.0:19; CHECK-GI-NEXT: smull x8, w2, w120; CHECK-GI-NEXT: smaddl x8, w4, w3, x821; CHECK-GI-NEXT: sub x0, x0, x822; CHECK-GI-NEXT: ret23 %be = sext i32 %b to i6424 %ce = sext i32 %c to i6425 %de = sext i32 %d to i6426 %ee = sext i32 %e to i6427 %m1.neg = mul nsw i64 %ce, %be28 %m2.neg = mul nsw i64 %ee, %de29 %reass.add = add i64 %m2.neg, %m1.neg30 %s2 = sub i64 %a, %reass.add31 ret i64 %s232}33 34define i64 @umlsl_i64(i64 %a, i32 %b, i32 %c, i32 %d, i32 %e) {35; CHECK-SD-LABEL: umlsl_i64:36; CHECK-SD: // %bb.0:37; CHECK-SD-NEXT: umsubl x8, w4, w3, x038; CHECK-SD-NEXT: umsubl x0, w2, w1, x839; CHECK-SD-NEXT: ret40;41; CHECK-GI-LABEL: umlsl_i64:42; CHECK-GI: // %bb.0:43; CHECK-GI-NEXT: umull x8, w2, w144; CHECK-GI-NEXT: umaddl x8, w4, w3, x845; CHECK-GI-NEXT: sub x0, x0, x846; CHECK-GI-NEXT: ret47 %be = zext i32 %b to i6448 %ce = zext i32 %c to i6449 %de = zext i32 %d to i6450 %ee = zext i32 %e to i6451 %m1.neg = mul nuw i64 %ce, %be52 %m2.neg = mul nuw i64 %ee, %de53 %reass.add = add i64 %m2.neg, %m1.neg54 %s2 = sub i64 %a, %reass.add55 ret i64 %s256}57 58define i64 @mls_i64(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {59; CHECK-SD-LABEL: mls_i64:60; CHECK-SD: // %bb.0:61; CHECK-SD-NEXT: msub x8, x4, x3, x062; CHECK-SD-NEXT: msub x0, x2, x1, x863; CHECK-SD-NEXT: ret64;65; CHECK-GI-LABEL: mls_i64:66; CHECK-GI: // %bb.0:67; CHECK-GI-NEXT: mul x8, x2, x168; CHECK-GI-NEXT: madd x8, x4, x3, x869; CHECK-GI-NEXT: sub x0, x0, x870; CHECK-GI-NEXT: ret71 %m1.neg = mul i64 %c, %b72 %m2.neg = mul i64 %e, %d73 %reass.add = add i64 %m2.neg, %m1.neg74 %s2 = sub i64 %a, %reass.add75 ret i64 %s276}77 78define i16 @mls_i16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e) {79; CHECK-SD-LABEL: mls_i16:80; CHECK-SD: // %bb.0:81; CHECK-SD-NEXT: msub w8, w4, w3, w082; CHECK-SD-NEXT: msub w0, w2, w1, w883; CHECK-SD-NEXT: ret84;85; CHECK-GI-LABEL: mls_i16:86; CHECK-GI: // %bb.0:87; CHECK-GI-NEXT: mul w8, w2, w188; CHECK-GI-NEXT: madd w8, w4, w3, w889; CHECK-GI-NEXT: sub w0, w0, w890; CHECK-GI-NEXT: ret91 %m1.neg = mul i16 %c, %b92 %m2.neg = mul i16 %e, %d93 %reass.add = add i16 %m2.neg, %m1.neg94 %s2 = sub i16 %a, %reass.add95 ret i16 %s296}97 98define i64 @mla_i64(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {99; CHECK-LABEL: mla_i64:100; CHECK: // %bb.0:101; CHECK-NEXT: mul x8, x4, x3102; CHECK-NEXT: madd x8, x2, x1, x8103; CHECK-NEXT: add x0, x8, x0104; CHECK-NEXT: ret105 %m1 = mul i64 %c, %b106 %m2 = mul i64 %e, %d107 %s1 = add i64 %m1, %m2108 %s2 = add i64 %s1, %a109 ret i64 %s2110}111 112define i64 @mls_i64_C(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {113; CHECK-LABEL: mls_i64_C:114; CHECK: // %bb.0:115; CHECK-NEXT: mul x8, x2, x1116; CHECK-NEXT: mov w9, #10 // =0xa117; CHECK-NEXT: madd x8, x4, x3, x8118; CHECK-NEXT: sub x0, x9, x8119; CHECK-NEXT: ret120 %m1.neg = mul i64 %c, %b121 %m2.neg = mul i64 %e, %d122 %reass.add = add i64 %m2.neg, %m1.neg123 %s2 = sub i64 10, %reass.add124 ret i64 %s2125}126 127define i64 @umlsl_i64_muls(i64 %a, i32 %b, i32 %c, i32 %d, i32 %e) {128; CHECK-SD-LABEL: umlsl_i64_muls:129; CHECK-SD: // %bb.0:130; CHECK-SD-NEXT: umull x8, w2, w3131; CHECK-SD-NEXT: umsubl x8, w4, w3, x8132; CHECK-SD-NEXT: umsubl x0, w2, w1, x8133; CHECK-SD-NEXT: ret134;135; CHECK-GI-LABEL: umlsl_i64_muls:136; CHECK-GI: // %bb.0:137; CHECK-GI-NEXT: umull x8, w2, w1138; CHECK-GI-NEXT: umull x9, w2, w3139; CHECK-GI-NEXT: umaddl x8, w4, w3, x8140; CHECK-GI-NEXT: sub x0, x9, x8141; CHECK-GI-NEXT: ret142 %be = zext i32 %b to i64143 %ce = zext i32 %c to i64144 %de = zext i32 %d to i64145 %ee = zext i32 %e to i64146 %m1.neg = mul nuw i64 %ce, %be147 %m2.neg = mul nuw i64 %ee, %de148 %m3 = mul nuw i64 %ce, %de149 %reass.add = add i64 %m2.neg, %m1.neg150 %s2 = sub i64 %m3, %reass.add151 ret i64 %s2152}153 154define i64 @umlsl_i64_uses(i64 %a, i32 %b, i32 %c, i32 %d, i32 %e) {155; CHECK-SD-LABEL: umlsl_i64_uses:156; CHECK-SD: // %bb.0:157; CHECK-SD-NEXT: umull x8, w4, w3158; CHECK-SD-NEXT: umaddl x8, w2, w1, x8159; CHECK-SD-NEXT: sub x9, x0, x8160; CHECK-SD-NEXT: and x0, x8, x9161; CHECK-SD-NEXT: ret162;163; CHECK-GI-LABEL: umlsl_i64_uses:164; CHECK-GI: // %bb.0:165; CHECK-GI-NEXT: umull x8, w2, w1166; CHECK-GI-NEXT: umaddl x8, w4, w3, x8167; CHECK-GI-NEXT: sub x9, x0, x8168; CHECK-GI-NEXT: and x0, x8, x9169; CHECK-GI-NEXT: ret170 %be = zext i32 %b to i64171 %ce = zext i32 %c to i64172 %de = zext i32 %d to i64173 %ee = zext i32 %e to i64174 %m1.neg = mul nuw i64 %ce, %be175 %m2.neg = mul nuw i64 %ee, %de176 %reass.add = add i64 %m2.neg, %m1.neg177 %s2 = sub i64 %a, %reass.add178 %o = and i64 %reass.add, %s2179 ret i64 %o180}181 182define i64 @mla_i64_C(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {183; CHECK-LABEL: mla_i64_C:184; CHECK: // %bb.0:185; CHECK-NEXT: mul x8, x2, x1186; CHECK-NEXT: madd x8, x4, x3, x8187; CHECK-NEXT: add x0, x8, #10188; CHECK-NEXT: ret189 %m1.neg = mul i64 %c, %b190 %m2.neg = mul i64 %e, %d191 %reass.add = add i64 %m2.neg, %m1.neg192 %s2 = add i64 10, %reass.add193 ret i64 %s2194}195 196define i64 @mla_i64_uses(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {197; CHECK-LABEL: mla_i64_uses:198; CHECK: // %bb.0:199; CHECK-NEXT: mul x8, x2, x1200; CHECK-NEXT: madd x8, x4, x3, x8201; CHECK-NEXT: add x9, x0, x8202; CHECK-NEXT: eor x0, x8, x9203; CHECK-NEXT: ret204 %m1.neg = mul i64 %c, %b205 %m2.neg = mul i64 %e, %d206 %reass.add = add i64 %m2.neg, %m1.neg207 %s2 = add i64 %a, %reass.add208 %o = xor i64 %reass.add, %s2209 ret i64 %o210}211 212define i64 @mla_i64_mul(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e) {213; CHECK-LABEL: mla_i64_mul:214; CHECK: // %bb.0:215; CHECK-NEXT: mul x8, x2, x1216; CHECK-NEXT: madd x9, x4, x3, x8217; CHECK-NEXT: add x0, x8, x9218; CHECK-NEXT: ret219 %m1.neg = mul i64 %c, %b220 %m2.neg = mul i64 %e, %d221 %reass.add = add i64 %m2.neg, %m1.neg222 %s2 = add i64 %m1.neg, %reass.add223 ret i64 %s2224}225 226 227define <8 x i16> @smlsl_v8i16(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d, <8 x i8> %e) {228; CHECK-SD-LABEL: smlsl_v8i16:229; CHECK-SD: // %bb.0:230; CHECK-SD-NEXT: smlsl v0.8h, v4.8b, v3.8b231; CHECK-SD-NEXT: smlsl v0.8h, v2.8b, v1.8b232; CHECK-SD-NEXT: ret233;234; CHECK-GI-LABEL: smlsl_v8i16:235; CHECK-GI: // %bb.0:236; CHECK-GI-NEXT: smull v1.8h, v2.8b, v1.8b237; CHECK-GI-NEXT: smlal v1.8h, v4.8b, v3.8b238; CHECK-GI-NEXT: sub v0.8h, v0.8h, v1.8h239; CHECK-GI-NEXT: ret240 %be = sext <8 x i8> %b to <8 x i16>241 %ce = sext <8 x i8> %c to <8 x i16>242 %de = sext <8 x i8> %d to <8 x i16>243 %ee = sext <8 x i8> %e to <8 x i16>244 %m1.neg = mul nsw <8 x i16> %ce, %be245 %m2.neg = mul nsw <8 x i16> %ee, %de246 %reass.add = add <8 x i16> %m2.neg, %m1.neg247 %s2 = sub <8 x i16> %a, %reass.add248 ret <8 x i16> %s2249}250 251define <8 x i16> @umlsl_v8i16(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d, <8 x i8> %e) {252; CHECK-SD-LABEL: umlsl_v8i16:253; CHECK-SD: // %bb.0:254; CHECK-SD-NEXT: umlsl v0.8h, v4.8b, v3.8b255; CHECK-SD-NEXT: umlsl v0.8h, v2.8b, v1.8b256; CHECK-SD-NEXT: ret257;258; CHECK-GI-LABEL: umlsl_v8i16:259; CHECK-GI: // %bb.0:260; CHECK-GI-NEXT: umull v1.8h, v2.8b, v1.8b261; CHECK-GI-NEXT: umlal v1.8h, v4.8b, v3.8b262; CHECK-GI-NEXT: sub v0.8h, v0.8h, v1.8h263; CHECK-GI-NEXT: ret264 %be = zext <8 x i8> %b to <8 x i16>265 %ce = zext <8 x i8> %c to <8 x i16>266 %de = zext <8 x i8> %d to <8 x i16>267 %ee = zext <8 x i8> %e to <8 x i16>268 %m1.neg = mul nuw <8 x i16> %ce, %be269 %m2.neg = mul nuw <8 x i16> %ee, %de270 %reass.add = add <8 x i16> %m2.neg, %m1.neg271 %s2 = sub <8 x i16> %a, %reass.add272 ret <8 x i16> %s2273}274 275define <8 x i16> @mls_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e) {276; CHECK-SD-LABEL: mls_v8i16:277; CHECK-SD: // %bb.0:278; CHECK-SD-NEXT: mls v0.8h, v4.8h, v3.8h279; CHECK-SD-NEXT: mls v0.8h, v2.8h, v1.8h280; CHECK-SD-NEXT: ret281;282; CHECK-GI-LABEL: mls_v8i16:283; CHECK-GI: // %bb.0:284; CHECK-GI-NEXT: mul v1.8h, v2.8h, v1.8h285; CHECK-GI-NEXT: mla v1.8h, v4.8h, v3.8h286; CHECK-GI-NEXT: sub v0.8h, v0.8h, v1.8h287; CHECK-GI-NEXT: ret288 %m1.neg = mul <8 x i16> %c, %b289 %m2.neg = mul <8 x i16> %e, %d290 %reass.add = add <8 x i16> %m2.neg, %m1.neg291 %s2 = sub <8 x i16> %a, %reass.add292 ret <8 x i16> %s2293}294 295define <8 x i16> @mla_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e) {296; CHECK-LABEL: mla_v8i16:297; CHECK: // %bb.0:298; CHECK-NEXT: mul v3.8h, v4.8h, v3.8h299; CHECK-NEXT: mla v3.8h, v2.8h, v1.8h300; CHECK-NEXT: add v0.8h, v3.8h, v0.8h301; CHECK-NEXT: ret302 %m1 = mul <8 x i16> %c, %b303 %m2 = mul <8 x i16> %e, %d304 %s1 = add <8 x i16> %m1, %m2305 %s2 = add <8 x i16> %s1, %a306 ret <8 x i16> %s2307}308 309define <8 x i16> @mls_v8i16_C(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e) {310; CHECK-SD-LABEL: mls_v8i16_C:311; CHECK-SD: // %bb.0:312; CHECK-SD-NEXT: movi v0.8h, #10313; CHECK-SD-NEXT: mls v0.8h, v4.8h, v3.8h314; CHECK-SD-NEXT: mls v0.8h, v2.8h, v1.8h315; CHECK-SD-NEXT: ret316;317; CHECK-GI-LABEL: mls_v8i16_C:318; CHECK-GI: // %bb.0:319; CHECK-GI-NEXT: mul v0.8h, v2.8h, v1.8h320; CHECK-GI-NEXT: movi v1.8h, #10321; CHECK-GI-NEXT: mla v0.8h, v4.8h, v3.8h322; CHECK-GI-NEXT: sub v0.8h, v1.8h, v0.8h323; CHECK-GI-NEXT: ret324 %m1.neg = mul <8 x i16> %c, %b325 %m2.neg = mul <8 x i16> %e, %d326 %reass.add = add <8 x i16> %m2.neg, %m1.neg327 %s2 = sub <8 x i16> <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>, %reass.add328 ret <8 x i16> %s2329}330 331define <8 x i16> @mla_v8i16_C(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d, <8 x i16> %e) {332; CHECK-SD-LABEL: mla_v8i16_C:333; CHECK-SD: // %bb.0:334; CHECK-SD-NEXT: mul v1.8h, v2.8h, v1.8h335; CHECK-SD-NEXT: movi v0.8h, #10336; CHECK-SD-NEXT: mla v1.8h, v4.8h, v3.8h337; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h338; CHECK-SD-NEXT: ret339;340; CHECK-GI-LABEL: mla_v8i16_C:341; CHECK-GI: // %bb.0:342; CHECK-GI-NEXT: mul v0.8h, v2.8h, v1.8h343; CHECK-GI-NEXT: movi v1.8h, #10344; CHECK-GI-NEXT: mla v0.8h, v4.8h, v3.8h345; CHECK-GI-NEXT: add v0.8h, v1.8h, v0.8h346; CHECK-GI-NEXT: ret347 %m1.neg = mul <8 x i16> %c, %b348 %m2.neg = mul <8 x i16> %e, %d349 %reass.add = add <8 x i16> %m2.neg, %m1.neg350 %s2 = add <8 x i16> <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>, %reass.add351 ret <8 x i16> %s2352}353 354 355define <vscale x 8 x i16> @smlsl_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e) {356; CHECK-LABEL: smlsl_nxv8i16:357; CHECK: // %bb.0:358; CHECK-NEXT: ptrue p0.h359; CHECK-NEXT: sxtb z3.h, p0/m, z3.h360; CHECK-NEXT: sxtb z4.h, p0/m, z4.h361; CHECK-NEXT: sxtb z1.h, p0/m, z1.h362; CHECK-NEXT: sxtb z2.h, p0/m, z2.h363; CHECK-NEXT: mls z0.h, p0/m, z4.h, z3.h364; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h365; CHECK-NEXT: ret366 %be = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>367 %ce = sext <vscale x 8 x i8> %c to <vscale x 8 x i16>368 %de = sext <vscale x 8 x i8> %d to <vscale x 8 x i16>369 %ee = sext <vscale x 8 x i8> %e to <vscale x 8 x i16>370 %m1.neg = mul nsw <vscale x 8 x i16> %ce, %be371 %m2.neg = mul nsw <vscale x 8 x i16> %ee, %de372 %reass.add = add <vscale x 8 x i16> %m2.neg, %m1.neg373 %s2 = sub <vscale x 8 x i16> %a, %reass.add374 ret <vscale x 8 x i16> %s2375}376 377define <vscale x 8 x i16> @umlsl_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, <vscale x 8 x i8> %d, <vscale x 8 x i8> %e) {378; CHECK-LABEL: umlsl_nxv8i16:379; CHECK: // %bb.0:380; CHECK-NEXT: and z3.h, z3.h, #0xff381; CHECK-NEXT: and z4.h, z4.h, #0xff382; CHECK-NEXT: ptrue p0.h383; CHECK-NEXT: and z1.h, z1.h, #0xff384; CHECK-NEXT: and z2.h, z2.h, #0xff385; CHECK-NEXT: mls z0.h, p0/m, z4.h, z3.h386; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h387; CHECK-NEXT: ret388 %be = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>389 %ce = zext <vscale x 8 x i8> %c to <vscale x 8 x i16>390 %de = zext <vscale x 8 x i8> %d to <vscale x 8 x i16>391 %ee = zext <vscale x 8 x i8> %e to <vscale x 8 x i16>392 %m1.neg = mul nuw <vscale x 8 x i16> %ce, %be393 %m2.neg = mul nuw <vscale x 8 x i16> %ee, %de394 %reass.add = add <vscale x 8 x i16> %m2.neg, %m1.neg395 %s2 = sub <vscale x 8 x i16> %a, %reass.add396 ret <vscale x 8 x i16> %s2397}398 399define <vscale x 8 x i16> @mls_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e) {400; CHECK-LABEL: mls_nxv8i16:401; CHECK: // %bb.0:402; CHECK-NEXT: ptrue p0.h403; CHECK-NEXT: mls z0.h, p0/m, z4.h, z3.h404; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h405; CHECK-NEXT: ret406 %m1.neg = mul <vscale x 8 x i16> %c, %b407 %m2.neg = mul <vscale x 8 x i16> %e, %d408 %reass.add = add <vscale x 8 x i16> %m2.neg, %m1.neg409 %s2 = sub <vscale x 8 x i16> %a, %reass.add410 ret <vscale x 8 x i16> %s2411}412 413define <vscale x 8 x i16> @mla_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i16> %d, <vscale x 8 x i16> %e) {414; CHECK-LABEL: mla_nxv8i16:415; CHECK: // %bb.0:416; CHECK-NEXT: mul z1.h, z2.h, z1.h417; CHECK-NEXT: ptrue p0.h418; CHECK-NEXT: mla z1.h, p0/m, z4.h, z3.h419; CHECK-NEXT: add z0.h, z1.h, z0.h420; CHECK-NEXT: ret421 %m1 = mul <vscale x 8 x i16> %c, %b422 %m2 = mul <vscale x 8 x i16> %e, %d423 %s1 = add <vscale x 8 x i16> %m1, %m2424 %s2 = add <vscale x 8 x i16> %s1, %a425 ret <vscale x 8 x i16> %s2426}427