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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+neon | FileCheck %s3; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL4 5 6define i1 @test_redand_v1i1(<1 x i1> %a) {7; CHECK-LABEL: test_redand_v1i1:8; CHECK: // %bb.0:9; CHECK-NEXT: and w0, w0, #0x110; CHECK-NEXT: ret11;12; GISEL-LABEL: test_redand_v1i1:13; GISEL: // %bb.0:14; GISEL-NEXT: and w0, w0, #0x115; GISEL-NEXT: ret16 %or_result = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)17 ret i1 %or_result18}19 20define i1 @test_redand_v2i1(<2 x i1> %a) {21; CHECK-LABEL: test_redand_v2i1:22; CHECK: // %bb.0:23; CHECK-NEXT: shl v0.2s, v0.2s, #3124; CHECK-NEXT: cmlt v0.2s, v0.2s, #025; CHECK-NEXT: uminp v0.2s, v0.2s, v0.2s26; CHECK-NEXT: fmov w8, s027; CHECK-NEXT: and w0, w8, #0x128; CHECK-NEXT: ret29;30; GISEL-LABEL: test_redand_v2i1:31; GISEL: // %bb.0:32; GISEL-NEXT: // kill: def $d0 killed $d0 def $q033; GISEL-NEXT: mov w8, v0.s[1]34; GISEL-NEXT: fmov w9, s035; GISEL-NEXT: and w8, w9, w836; GISEL-NEXT: and w0, w8, #0x137; GISEL-NEXT: ret38 %or_result = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %a)39 ret i1 %or_result40}41 42define i1 @test_redand_v4i1(<4 x i1> %a) {43; CHECK-LABEL: test_redand_v4i1:44; CHECK: // %bb.0:45; CHECK-NEXT: shl v0.4h, v0.4h, #1546; CHECK-NEXT: cmlt v0.4h, v0.4h, #047; CHECK-NEXT: uminv h0, v0.4h48; CHECK-NEXT: fmov w8, s049; CHECK-NEXT: and w0, w8, #0x150; CHECK-NEXT: ret51;52; GISEL-LABEL: test_redand_v4i1:53; GISEL: // %bb.0:54; GISEL-NEXT: // kill: def $d0 killed $d0 def $q055; GISEL-NEXT: umov w8, v0.h[0]56; GISEL-NEXT: umov w9, v0.h[1]57; GISEL-NEXT: umov w10, v0.h[2]58; GISEL-NEXT: umov w11, v0.h[3]59; GISEL-NEXT: and w8, w8, w960; GISEL-NEXT: and w9, w10, w1161; GISEL-NEXT: and w8, w8, w962; GISEL-NEXT: and w0, w8, #0x163; GISEL-NEXT: ret64 %or_result = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)65 ret i1 %or_result66}67 68define i1 @test_redand_v8i1(<8 x i1> %a) {69; CHECK-LABEL: test_redand_v8i1:70; CHECK: // %bb.0:71; CHECK-NEXT: shl v0.8b, v0.8b, #772; CHECK-NEXT: cmlt v0.8b, v0.8b, #073; CHECK-NEXT: uminv b0, v0.8b74; CHECK-NEXT: fmov w8, s075; CHECK-NEXT: and w0, w8, #0x176; CHECK-NEXT: ret77;78; GISEL-LABEL: test_redand_v8i1:79; GISEL: // %bb.0:80; GISEL-NEXT: // kill: def $d0 killed $d0 def $q081; GISEL-NEXT: umov w8, v0.b[0]82; GISEL-NEXT: umov w9, v0.b[1]83; GISEL-NEXT: umov w10, v0.b[2]84; GISEL-NEXT: umov w11, v0.b[3]85; GISEL-NEXT: umov w12, v0.b[4]86; GISEL-NEXT: umov w13, v0.b[5]87; GISEL-NEXT: umov w14, v0.b[6]88; GISEL-NEXT: umov w15, v0.b[7]89; GISEL-NEXT: and w8, w8, w990; GISEL-NEXT: and w9, w10, w1191; GISEL-NEXT: and w10, w12, w1392; GISEL-NEXT: and w11, w14, w1593; GISEL-NEXT: and w8, w8, w994; GISEL-NEXT: and w9, w10, w1195; GISEL-NEXT: and w8, w8, w996; GISEL-NEXT: and w0, w8, #0x197; GISEL-NEXT: ret98 %or_result = call i1 @llvm.vector.reduce.and.v8i1(<8 x i1> %a)99 ret i1 %or_result100}101 102define i1 @test_redand_v16i1(<16 x i1> %a) {103; CHECK-LABEL: test_redand_v16i1:104; CHECK: // %bb.0:105; CHECK-NEXT: shl v0.16b, v0.16b, #7106; CHECK-NEXT: cmlt v0.16b, v0.16b, #0107; CHECK-NEXT: uminv b0, v0.16b108; CHECK-NEXT: fmov w8, s0109; CHECK-NEXT: and w0, w8, #0x1110; CHECK-NEXT: ret111;112; GISEL-LABEL: test_redand_v16i1:113; GISEL: // %bb.0:114; GISEL-NEXT: umov w8, v0.b[0]115; GISEL-NEXT: umov w9, v0.b[1]116; GISEL-NEXT: umov w10, v0.b[2]117; GISEL-NEXT: umov w11, v0.b[3]118; GISEL-NEXT: umov w12, v0.b[4]119; GISEL-NEXT: umov w13, v0.b[5]120; GISEL-NEXT: umov w14, v0.b[6]121; GISEL-NEXT: umov w15, v0.b[7]122; GISEL-NEXT: umov w16, v0.b[8]123; GISEL-NEXT: umov w17, v0.b[9]124; GISEL-NEXT: umov w18, v0.b[10]125; GISEL-NEXT: umov w0, v0.b[11]126; GISEL-NEXT: and w8, w8, w9127; GISEL-NEXT: umov w1, v0.b[12]128; GISEL-NEXT: umov w2, v0.b[13]129; GISEL-NEXT: and w9, w10, w11130; GISEL-NEXT: and w10, w12, w13131; GISEL-NEXT: umov w3, v0.b[14]132; GISEL-NEXT: and w11, w14, w15133; GISEL-NEXT: and w8, w8, w9134; GISEL-NEXT: umov w4, v0.b[15]135; GISEL-NEXT: and w12, w16, w17136; GISEL-NEXT: and w13, w18, w0137; GISEL-NEXT: and w9, w10, w11138; GISEL-NEXT: and w14, w1, w2139; GISEL-NEXT: and w10, w12, w13140; GISEL-NEXT: and w8, w8, w9141; GISEL-NEXT: and w15, w3, w4142; GISEL-NEXT: and w11, w14, w15143; GISEL-NEXT: and w9, w10, w11144; GISEL-NEXT: and w8, w8, w9145; GISEL-NEXT: and w0, w8, #0x1146; GISEL-NEXT: ret147 %or_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)148 ret i1 %or_result149}150 151define <16 x i1> @test_redand_ins_v16i1(<16 x i1> %a) {152; CHECK-LABEL: test_redand_ins_v16i1:153; CHECK: // %bb.0:154; CHECK-NEXT: shl v0.16b, v0.16b, #7155; CHECK-NEXT: cmlt v0.16b, v0.16b, #0156; CHECK-NEXT: uminv b0, v0.16b157; CHECK-NEXT: ret158;159; GISEL-LABEL: test_redand_ins_v16i1:160; GISEL: // %bb.0:161; GISEL-NEXT: umov w8, v0.b[0]162; GISEL-NEXT: umov w9, v0.b[1]163; GISEL-NEXT: umov w10, v0.b[2]164; GISEL-NEXT: umov w11, v0.b[3]165; GISEL-NEXT: umov w12, v0.b[4]166; GISEL-NEXT: umov w13, v0.b[5]167; GISEL-NEXT: umov w14, v0.b[6]168; GISEL-NEXT: umov w15, v0.b[7]169; GISEL-NEXT: umov w16, v0.b[8]170; GISEL-NEXT: umov w17, v0.b[9]171; GISEL-NEXT: umov w18, v0.b[10]172; GISEL-NEXT: umov w0, v0.b[11]173; GISEL-NEXT: and w8, w8, w9174; GISEL-NEXT: umov w1, v0.b[12]175; GISEL-NEXT: umov w2, v0.b[13]176; GISEL-NEXT: and w9, w10, w11177; GISEL-NEXT: and w10, w12, w13178; GISEL-NEXT: umov w3, v0.b[14]179; GISEL-NEXT: and w11, w14, w15180; GISEL-NEXT: and w8, w8, w9181; GISEL-NEXT: umov w4, v0.b[15]182; GISEL-NEXT: and w12, w16, w17183; GISEL-NEXT: and w13, w18, w0184; GISEL-NEXT: and w9, w10, w11185; GISEL-NEXT: and w14, w1, w2186; GISEL-NEXT: and w10, w12, w13187; GISEL-NEXT: and w8, w8, w9188; GISEL-NEXT: and w15, w3, w4189; GISEL-NEXT: and w11, w14, w15190; GISEL-NEXT: and w9, w10, w11191; GISEL-NEXT: and w8, w8, w9192; GISEL-NEXT: fmov s0, w8193; GISEL-NEXT: ret194 %and_result = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %a)195 %ins = insertelement <16 x i1> poison, i1 %and_result, i64 0196 ret <16 x i1> %ins197}198 199define i8 @test_redand_v1i8(<1 x i8> %a) {200; CHECK-LABEL: test_redand_v1i8:201; CHECK: // %bb.0:202; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0203; CHECK-NEXT: umov w0, v0.b[0]204; CHECK-NEXT: ret205;206; GISEL-LABEL: test_redand_v1i8:207; GISEL: // %bb.0:208; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0209; GISEL-NEXT: umov w0, v0.b[0]210; GISEL-NEXT: ret211 %and_result = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)212 ret i8 %and_result213}214 215define i8 @test_redand_v3i8(<3 x i8> %a) {216; CHECK-LABEL: test_redand_v3i8:217; CHECK: // %bb.0:218; CHECK-NEXT: movi d0, #0xff00ff00ff00ff219; CHECK-NEXT: mov v0.h[0], w0220; CHECK-NEXT: mov v0.h[1], w1221; CHECK-NEXT: mov v0.h[2], w2222; CHECK-NEXT: fmov x8, d0223; CHECK-NEXT: and x8, x8, x8, lsr #32224; CHECK-NEXT: lsr x9, x8, #16225; CHECK-NEXT: and w0, w8, w9226; CHECK-NEXT: ret227;228; GISEL-LABEL: test_redand_v3i8:229; GISEL: // %bb.0:230; GISEL-NEXT: and w8, w0, w1231; GISEL-NEXT: and w0, w8, w2232; GISEL-NEXT: ret233 %and_result = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)234 ret i8 %and_result235}236 237define i8 @test_redand_v4i8(<4 x i8> %a) {238; CHECK-LABEL: test_redand_v4i8:239; CHECK: // %bb.0:240; CHECK-NEXT: fmov x8, d0241; CHECK-NEXT: and x8, x8, x8, lsr #32242; CHECK-NEXT: lsr x9, x8, #16243; CHECK-NEXT: and w0, w8, w9244; CHECK-NEXT: ret245;246; GISEL-LABEL: test_redand_v4i8:247; GISEL: // %bb.0:248; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0249; GISEL-NEXT: umov w8, v0.h[0]250; GISEL-NEXT: umov w9, v0.h[1]251; GISEL-NEXT: umov w10, v0.h[2]252; GISEL-NEXT: umov w11, v0.h[3]253; GISEL-NEXT: and w8, w8, w9254; GISEL-NEXT: and w9, w10, w11255; GISEL-NEXT: and w0, w8, w9256; GISEL-NEXT: ret257 %and_result = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %a)258 ret i8 %and_result259}260 261define i8 @test_redand_v8i8(<8 x i8> %a) {262; CHECK-LABEL: test_redand_v8i8:263; CHECK: // %bb.0:264; CHECK-NEXT: fmov x8, d0265; CHECK-NEXT: and x8, x8, x8, lsr #32266; CHECK-NEXT: and x8, x8, x8, lsr #16267; CHECK-NEXT: lsr x9, x8, #8268; CHECK-NEXT: and w0, w8, w9269; CHECK-NEXT: ret270;271; GISEL-LABEL: test_redand_v8i8:272; GISEL: // %bb.0:273; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0274; GISEL-NEXT: umov w8, v0.b[0]275; GISEL-NEXT: umov w9, v0.b[1]276; GISEL-NEXT: umov w10, v0.b[2]277; GISEL-NEXT: umov w11, v0.b[3]278; GISEL-NEXT: umov w12, v0.b[4]279; GISEL-NEXT: umov w13, v0.b[5]280; GISEL-NEXT: umov w14, v0.b[6]281; GISEL-NEXT: umov w15, v0.b[7]282; GISEL-NEXT: and w8, w8, w9283; GISEL-NEXT: and w9, w10, w11284; GISEL-NEXT: and w10, w12, w13285; GISEL-NEXT: and w11, w14, w15286; GISEL-NEXT: and w8, w8, w9287; GISEL-NEXT: and w9, w10, w11288; GISEL-NEXT: and w0, w8, w9289; GISEL-NEXT: ret290 %and_result = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %a)291 ret i8 %and_result292}293 294define i8 @test_redand_v16i8(<16 x i8> %a) {295; CHECK-LABEL: test_redand_v16i8:296; CHECK: // %bb.0:297; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8298; CHECK-NEXT: and v0.8b, v0.8b, v1.8b299; CHECK-NEXT: fmov x8, d0300; CHECK-NEXT: and x8, x8, x8, lsr #32301; CHECK-NEXT: and x8, x8, x8, lsr #16302; CHECK-NEXT: lsr x9, x8, #8303; CHECK-NEXT: and w0, w8, w9304; CHECK-NEXT: ret305;306; GISEL-LABEL: test_redand_v16i8:307; GISEL: // %bb.0:308; GISEL-NEXT: mov d1, v0.d[1]309; GISEL-NEXT: and v0.8b, v0.8b, v1.8b310; GISEL-NEXT: umov w8, v0.b[0]311; GISEL-NEXT: umov w9, v0.b[1]312; GISEL-NEXT: umov w10, v0.b[2]313; GISEL-NEXT: umov w11, v0.b[3]314; GISEL-NEXT: umov w12, v0.b[4]315; GISEL-NEXT: umov w13, v0.b[5]316; GISEL-NEXT: umov w14, v0.b[6]317; GISEL-NEXT: umov w15, v0.b[7]318; GISEL-NEXT: and w8, w8, w9319; GISEL-NEXT: and w9, w10, w11320; GISEL-NEXT: and w10, w12, w13321; GISEL-NEXT: and w11, w14, w15322; GISEL-NEXT: and w8, w8, w9323; GISEL-NEXT: and w9, w10, w11324; GISEL-NEXT: and w0, w8, w9325; GISEL-NEXT: ret326 %and_result = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %a)327 ret i8 %and_result328}329 330define i8 @test_redand_v32i8(<32 x i8> %a) {331; CHECK-LABEL: test_redand_v32i8:332; CHECK: // %bb.0:333; CHECK-NEXT: and v0.16b, v0.16b, v1.16b334; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8335; CHECK-NEXT: and v0.8b, v0.8b, v1.8b336; CHECK-NEXT: fmov x8, d0337; CHECK-NEXT: and x8, x8, x8, lsr #32338; CHECK-NEXT: and x8, x8, x8, lsr #16339; CHECK-NEXT: lsr x9, x8, #8340; CHECK-NEXT: and w0, w8, w9341; CHECK-NEXT: ret342;343; GISEL-LABEL: test_redand_v32i8:344; GISEL: // %bb.0:345; GISEL-NEXT: and v0.16b, v0.16b, v1.16b346; GISEL-NEXT: mov d1, v0.d[1]347; GISEL-NEXT: and v0.8b, v0.8b, v1.8b348; GISEL-NEXT: umov w8, v0.b[0]349; GISEL-NEXT: umov w9, v0.b[1]350; GISEL-NEXT: umov w10, v0.b[2]351; GISEL-NEXT: umov w11, v0.b[3]352; GISEL-NEXT: umov w12, v0.b[4]353; GISEL-NEXT: umov w13, v0.b[5]354; GISEL-NEXT: umov w14, v0.b[6]355; GISEL-NEXT: umov w15, v0.b[7]356; GISEL-NEXT: and w8, w8, w9357; GISEL-NEXT: and w9, w10, w11358; GISEL-NEXT: and w10, w12, w13359; GISEL-NEXT: and w11, w14, w15360; GISEL-NEXT: and w8, w8, w9361; GISEL-NEXT: and w9, w10, w11362; GISEL-NEXT: and w0, w8, w9363; GISEL-NEXT: ret364 %and_result = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %a)365 ret i8 %and_result366}367 368define i16 @test_redand_v4i16(<4 x i16> %a) {369; CHECK-LABEL: test_redand_v4i16:370; CHECK: // %bb.0:371; CHECK-NEXT: fmov x8, d0372; CHECK-NEXT: and x8, x8, x8, lsr #32373; CHECK-NEXT: lsr x9, x8, #16374; CHECK-NEXT: and w0, w8, w9375; CHECK-NEXT: ret376;377; GISEL-LABEL: test_redand_v4i16:378; GISEL: // %bb.0:379; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0380; GISEL-NEXT: umov w8, v0.h[0]381; GISEL-NEXT: umov w9, v0.h[1]382; GISEL-NEXT: umov w10, v0.h[2]383; GISEL-NEXT: umov w11, v0.h[3]384; GISEL-NEXT: and w8, w8, w9385; GISEL-NEXT: and w9, w10, w11386; GISEL-NEXT: and w0, w8, w9387; GISEL-NEXT: ret388 %and_result = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %a)389 ret i16 %and_result390}391 392define i16 @test_redand_v8i16(<8 x i16> %a) {393; CHECK-LABEL: test_redand_v8i16:394; CHECK: // %bb.0:395; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8396; CHECK-NEXT: and v0.8b, v0.8b, v1.8b397; CHECK-NEXT: fmov x8, d0398; CHECK-NEXT: and x8, x8, x8, lsr #32399; CHECK-NEXT: lsr x9, x8, #16400; CHECK-NEXT: and w0, w8, w9401; CHECK-NEXT: ret402;403; GISEL-LABEL: test_redand_v8i16:404; GISEL: // %bb.0:405; GISEL-NEXT: mov d1, v0.d[1]406; GISEL-NEXT: and v0.8b, v0.8b, v1.8b407; GISEL-NEXT: umov w8, v0.h[0]408; GISEL-NEXT: umov w9, v0.h[1]409; GISEL-NEXT: umov w10, v0.h[2]410; GISEL-NEXT: umov w11, v0.h[3]411; GISEL-NEXT: and w8, w8, w9412; GISEL-NEXT: and w9, w10, w11413; GISEL-NEXT: and w0, w8, w9414; GISEL-NEXT: ret415 %and_result = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %a)416 ret i16 %and_result417}418 419define i16 @test_redand_v16i16(<16 x i16> %a) {420; CHECK-LABEL: test_redand_v16i16:421; CHECK: // %bb.0:422; CHECK-NEXT: and v0.16b, v0.16b, v1.16b423; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8424; CHECK-NEXT: and v0.8b, v0.8b, v1.8b425; CHECK-NEXT: fmov x8, d0426; CHECK-NEXT: and x8, x8, x8, lsr #32427; CHECK-NEXT: lsr x9, x8, #16428; CHECK-NEXT: and w0, w8, w9429; CHECK-NEXT: ret430;431; GISEL-LABEL: test_redand_v16i16:432; GISEL: // %bb.0:433; GISEL-NEXT: and v0.16b, v0.16b, v1.16b434; GISEL-NEXT: mov d1, v0.d[1]435; GISEL-NEXT: and v0.8b, v0.8b, v1.8b436; GISEL-NEXT: umov w8, v0.h[0]437; GISEL-NEXT: umov w9, v0.h[1]438; GISEL-NEXT: umov w10, v0.h[2]439; GISEL-NEXT: umov w11, v0.h[3]440; GISEL-NEXT: and w8, w8, w9441; GISEL-NEXT: and w9, w10, w11442; GISEL-NEXT: and w0, w8, w9443; GISEL-NEXT: ret444 %and_result = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %a)445 ret i16 %and_result446}447 448define i32 @test_redand_v2i32(<2 x i32> %a) {449; CHECK-LABEL: test_redand_v2i32:450; CHECK: // %bb.0:451; CHECK-NEXT: fmov x8, d0452; CHECK-NEXT: lsr x9, x8, #32453; CHECK-NEXT: and w0, w8, w9454; CHECK-NEXT: ret455;456; GISEL-LABEL: test_redand_v2i32:457; GISEL: // %bb.0:458; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0459; GISEL-NEXT: mov w8, v0.s[1]460; GISEL-NEXT: fmov w9, s0461; GISEL-NEXT: and w0, w9, w8462; GISEL-NEXT: ret463 %and_result = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a)464 ret i32 %and_result465}466 467define i32 @test_redand_v4i32(<4 x i32> %a) {468; CHECK-LABEL: test_redand_v4i32:469; CHECK: // %bb.0:470; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8471; CHECK-NEXT: and v0.8b, v0.8b, v1.8b472; CHECK-NEXT: fmov x8, d0473; CHECK-NEXT: lsr x9, x8, #32474; CHECK-NEXT: and w0, w8, w9475; CHECK-NEXT: ret476;477; GISEL-LABEL: test_redand_v4i32:478; GISEL: // %bb.0:479; GISEL-NEXT: mov d1, v0.d[1]480; GISEL-NEXT: and v0.8b, v0.8b, v1.8b481; GISEL-NEXT: mov w8, v0.s[1]482; GISEL-NEXT: fmov w9, s0483; GISEL-NEXT: and w0, w9, w8484; GISEL-NEXT: ret485 %and_result = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)486 ret i32 %and_result487}488 489define i32 @test_redand_v8i32(<8 x i32> %a) {490; CHECK-LABEL: test_redand_v8i32:491; CHECK: // %bb.0:492; CHECK-NEXT: and v0.16b, v0.16b, v1.16b493; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8494; CHECK-NEXT: and v0.8b, v0.8b, v1.8b495; CHECK-NEXT: fmov x8, d0496; CHECK-NEXT: lsr x9, x8, #32497; CHECK-NEXT: and w0, w8, w9498; CHECK-NEXT: ret499;500; GISEL-LABEL: test_redand_v8i32:501; GISEL: // %bb.0:502; GISEL-NEXT: and v0.16b, v0.16b, v1.16b503; GISEL-NEXT: mov d1, v0.d[1]504; GISEL-NEXT: and v0.8b, v0.8b, v1.8b505; GISEL-NEXT: mov w8, v0.s[1]506; GISEL-NEXT: fmov w9, s0507; GISEL-NEXT: and w0, w9, w8508; GISEL-NEXT: ret509 %and_result = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %a)510 ret i32 %and_result511}512 513define i64 @test_redand_v2i64(<2 x i64> %a) {514; CHECK-LABEL: test_redand_v2i64:515; CHECK: // %bb.0:516; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8517; CHECK-NEXT: and v0.8b, v0.8b, v1.8b518; CHECK-NEXT: fmov x0, d0519; CHECK-NEXT: ret520;521; GISEL-LABEL: test_redand_v2i64:522; GISEL: // %bb.0:523; GISEL-NEXT: mov x8, v0.d[1]524; GISEL-NEXT: fmov x9, d0525; GISEL-NEXT: and x0, x9, x8526; GISEL-NEXT: ret527 %and_result = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %a)528 ret i64 %and_result529}530 531define i64 @test_redand_v4i64(<4 x i64> %a) {532; CHECK-LABEL: test_redand_v4i64:533; CHECK: // %bb.0:534; CHECK-NEXT: and v0.16b, v0.16b, v1.16b535; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8536; CHECK-NEXT: and v0.8b, v0.8b, v1.8b537; CHECK-NEXT: fmov x0, d0538; CHECK-NEXT: ret539;540; GISEL-LABEL: test_redand_v4i64:541; GISEL: // %bb.0:542; GISEL-NEXT: and v0.16b, v0.16b, v1.16b543; GISEL-NEXT: mov x8, v0.d[1]544; GISEL-NEXT: fmov x9, d0545; GISEL-NEXT: and x0, x9, x8546; GISEL-NEXT: ret547 %and_result = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %a)548 ret i64 %and_result549}550 551declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)552declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)553declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)554declare i1 @llvm.vector.reduce.and.v8i1(<8 x i1>)555declare i1 @llvm.vector.reduce.and.v16i1(<16 x i1>)556declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)557declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)558declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)559declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)560declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)561declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)562declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)563declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)564declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8>)565declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8>)566declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)567declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)568declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)569declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)570