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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s3; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL4 5 6define i1 @test_redor_v1i1(<1 x i1> %a) {7; CHECK-LABEL: test_redor_v1i1:8; CHECK: // %bb.0:9; CHECK-NEXT: and w0, w0, #0x110; CHECK-NEXT: ret11;12; GISEL-LABEL: test_redor_v1i1:13; GISEL: // %bb.0:14; GISEL-NEXT: and w0, w0, #0x115; GISEL-NEXT: ret16 %or_result = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a)17 ret i1 %or_result18}19 20define i1 @test_redor_v2i1(<2 x i1> %a) {21; CHECK-LABEL: test_redor_v2i1:22; CHECK: // %bb.0:23; CHECK-NEXT: shl v0.2s, v0.2s, #3124; CHECK-NEXT: cmlt v0.2s, v0.2s, #025; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s26; CHECK-NEXT: fmov w8, s027; CHECK-NEXT: and w0, w8, #0x128; CHECK-NEXT: ret29;30; GISEL-LABEL: test_redor_v2i1:31; GISEL: // %bb.0:32; GISEL-NEXT: // kill: def $d0 killed $d0 def $q033; GISEL-NEXT: mov w8, v0.s[1]34; GISEL-NEXT: fmov w9, s035; GISEL-NEXT: orr w8, w9, w836; GISEL-NEXT: and w0, w8, #0x137; GISEL-NEXT: ret38 %or_result = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %a)39 ret i1 %or_result40}41 42define i1 @test_redor_v4i1(<4 x i1> %a) {43; CHECK-LABEL: test_redor_v4i1:44; CHECK: // %bb.0:45; CHECK-NEXT: shl v0.4h, v0.4h, #1546; CHECK-NEXT: cmlt v0.4h, v0.4h, #047; CHECK-NEXT: umaxv h0, v0.4h48; CHECK-NEXT: fmov w8, s049; CHECK-NEXT: and w0, w8, #0x150; CHECK-NEXT: ret51;52; GISEL-LABEL: test_redor_v4i1:53; GISEL: // %bb.0:54; GISEL-NEXT: // kill: def $d0 killed $d0 def $q055; GISEL-NEXT: umov w8, v0.h[0]56; GISEL-NEXT: umov w9, v0.h[1]57; GISEL-NEXT: umov w10, v0.h[2]58; GISEL-NEXT: umov w11, v0.h[3]59; GISEL-NEXT: orr w8, w8, w960; GISEL-NEXT: orr w9, w10, w1161; GISEL-NEXT: orr w8, w8, w962; GISEL-NEXT: and w0, w8, #0x163; GISEL-NEXT: ret64 %or_result = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %a)65 ret i1 %or_result66}67 68define i1 @test_redor_v8i1(<8 x i1> %a) {69; CHECK-LABEL: test_redor_v8i1:70; CHECK: // %bb.0:71; CHECK-NEXT: shl v0.8b, v0.8b, #772; CHECK-NEXT: cmlt v0.8b, v0.8b, #073; CHECK-NEXT: umaxv b0, v0.8b74; CHECK-NEXT: fmov w8, s075; CHECK-NEXT: and w0, w8, #0x176; CHECK-NEXT: ret77;78; GISEL-LABEL: test_redor_v8i1:79; GISEL: // %bb.0:80; GISEL-NEXT: // kill: def $d0 killed $d0 def $q081; GISEL-NEXT: umov w8, v0.b[0]82; GISEL-NEXT: umov w9, v0.b[1]83; GISEL-NEXT: umov w10, v0.b[2]84; GISEL-NEXT: umov w11, v0.b[3]85; GISEL-NEXT: umov w12, v0.b[4]86; GISEL-NEXT: umov w13, v0.b[5]87; GISEL-NEXT: umov w14, v0.b[6]88; GISEL-NEXT: umov w15, v0.b[7]89; GISEL-NEXT: orr w8, w8, w990; GISEL-NEXT: orr w9, w10, w1191; GISEL-NEXT: orr w10, w12, w1392; GISEL-NEXT: orr w11, w14, w1593; GISEL-NEXT: orr w8, w8, w994; GISEL-NEXT: orr w9, w10, w1195; GISEL-NEXT: orr w8, w8, w996; GISEL-NEXT: and w0, w8, #0x197; GISEL-NEXT: ret98 %or_result = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %a)99 ret i1 %or_result100}101 102define i1 @test_redor_v16i1(<16 x i1> %a) {103; CHECK-LABEL: test_redor_v16i1:104; CHECK: // %bb.0:105; CHECK-NEXT: shl v0.16b, v0.16b, #7106; CHECK-NEXT: cmlt v0.16b, v0.16b, #0107; CHECK-NEXT: umaxv b0, v0.16b108; CHECK-NEXT: fmov w8, s0109; CHECK-NEXT: and w0, w8, #0x1110; CHECK-NEXT: ret111;112; GISEL-LABEL: test_redor_v16i1:113; GISEL: // %bb.0:114; GISEL-NEXT: umov w8, v0.b[0]115; GISEL-NEXT: umov w9, v0.b[1]116; GISEL-NEXT: umov w10, v0.b[2]117; GISEL-NEXT: umov w11, v0.b[3]118; GISEL-NEXT: umov w12, v0.b[4]119; GISEL-NEXT: umov w13, v0.b[5]120; GISEL-NEXT: umov w14, v0.b[6]121; GISEL-NEXT: umov w15, v0.b[7]122; GISEL-NEXT: umov w16, v0.b[8]123; GISEL-NEXT: umov w17, v0.b[9]124; GISEL-NEXT: umov w18, v0.b[10]125; GISEL-NEXT: umov w0, v0.b[11]126; GISEL-NEXT: orr w8, w8, w9127; GISEL-NEXT: umov w1, v0.b[12]128; GISEL-NEXT: umov w2, v0.b[13]129; GISEL-NEXT: orr w9, w10, w11130; GISEL-NEXT: orr w10, w12, w13131; GISEL-NEXT: umov w3, v0.b[14]132; GISEL-NEXT: orr w11, w14, w15133; GISEL-NEXT: orr w8, w8, w9134; GISEL-NEXT: umov w4, v0.b[15]135; GISEL-NEXT: orr w12, w16, w17136; GISEL-NEXT: orr w13, w18, w0137; GISEL-NEXT: orr w9, w10, w11138; GISEL-NEXT: orr w14, w1, w2139; GISEL-NEXT: orr w10, w12, w13140; GISEL-NEXT: orr w8, w8, w9141; GISEL-NEXT: orr w15, w3, w4142; GISEL-NEXT: orr w11, w14, w15143; GISEL-NEXT: orr w9, w10, w11144; GISEL-NEXT: orr w8, w8, w9145; GISEL-NEXT: and w0, w8, #0x1146; GISEL-NEXT: ret147 %or_result = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)148 ret i1 %or_result149}150 151define <16 x i1> @test_redor_ins_v16i1(<16 x i1> %a) {152; CHECK-LABEL: test_redor_ins_v16i1:153; CHECK: // %bb.0:154; CHECK-NEXT: shl v0.16b, v0.16b, #7155; CHECK-NEXT: cmlt v0.16b, v0.16b, #0156; CHECK-NEXT: umaxv b0, v0.16b157; CHECK-NEXT: ret158;159; GISEL-LABEL: test_redor_ins_v16i1:160; GISEL: // %bb.0:161; GISEL-NEXT: umov w8, v0.b[0]162; GISEL-NEXT: umov w9, v0.b[1]163; GISEL-NEXT: umov w10, v0.b[2]164; GISEL-NEXT: umov w11, v0.b[3]165; GISEL-NEXT: umov w12, v0.b[4]166; GISEL-NEXT: umov w13, v0.b[5]167; GISEL-NEXT: umov w14, v0.b[6]168; GISEL-NEXT: umov w15, v0.b[7]169; GISEL-NEXT: umov w16, v0.b[8]170; GISEL-NEXT: umov w17, v0.b[9]171; GISEL-NEXT: umov w18, v0.b[10]172; GISEL-NEXT: umov w0, v0.b[11]173; GISEL-NEXT: orr w8, w8, w9174; GISEL-NEXT: umov w1, v0.b[12]175; GISEL-NEXT: umov w2, v0.b[13]176; GISEL-NEXT: orr w9, w10, w11177; GISEL-NEXT: orr w10, w12, w13178; GISEL-NEXT: umov w3, v0.b[14]179; GISEL-NEXT: orr w11, w14, w15180; GISEL-NEXT: orr w8, w8, w9181; GISEL-NEXT: umov w4, v0.b[15]182; GISEL-NEXT: orr w12, w16, w17183; GISEL-NEXT: orr w13, w18, w0184; GISEL-NEXT: orr w9, w10, w11185; GISEL-NEXT: orr w14, w1, w2186; GISEL-NEXT: orr w10, w12, w13187; GISEL-NEXT: orr w8, w8, w9188; GISEL-NEXT: orr w15, w3, w4189; GISEL-NEXT: orr w11, w14, w15190; GISEL-NEXT: orr w9, w10, w11191; GISEL-NEXT: orr w8, w8, w9192; GISEL-NEXT: fmov s0, w8193; GISEL-NEXT: ret194 %or_result = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)195 %ins = insertelement <16 x i1> poison, i1 %or_result, i64 0196 ret <16 x i1> %ins197}198 199define i8 @test_redor_v1i8(<1 x i8> %a) {200; CHECK-LABEL: test_redor_v1i8:201; CHECK: // %bb.0:202; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0203; CHECK-NEXT: umov w0, v0.b[0]204; CHECK-NEXT: ret205;206; GISEL-LABEL: test_redor_v1i8:207; GISEL: // %bb.0:208; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0209; GISEL-NEXT: umov w0, v0.b[0]210; GISEL-NEXT: ret211 %or_result = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %a)212 ret i8 %or_result213}214 215define i8 @test_redor_v3i8(<3 x i8> %a) {216; CHECK-LABEL: test_redor_v3i8:217; CHECK: // %bb.0:218; CHECK-NEXT: movi v0.2d, #0000000000000000219; CHECK-NEXT: mov v0.h[0], w0220; CHECK-NEXT: mov v0.h[1], w1221; CHECK-NEXT: fmov x8, d0222; CHECK-NEXT: mov v0.h[2], w2223; CHECK-NEXT: fmov x9, d0224; CHECK-NEXT: lsr x10, x9, #32225; CHECK-NEXT: lsr x9, x9, #16226; CHECK-NEXT: orr w8, w8, w10227; CHECK-NEXT: orr w0, w8, w9228; CHECK-NEXT: ret229;230; GISEL-LABEL: test_redor_v3i8:231; GISEL: // %bb.0:232; GISEL-NEXT: orr w8, w0, w1233; GISEL-NEXT: orr w0, w8, w2234; GISEL-NEXT: ret235 %or_result = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> %a)236 ret i8 %or_result237}238 239define i8 @test_redor_v4i8(<4 x i8> %a) {240; CHECK-LABEL: test_redor_v4i8:241; CHECK: // %bb.0:242; CHECK-NEXT: fmov x8, d0243; CHECK-NEXT: orr x8, x8, x8, lsr #32244; CHECK-NEXT: lsr x9, x8, #16245; CHECK-NEXT: orr w0, w8, w9246; CHECK-NEXT: ret247;248; GISEL-LABEL: test_redor_v4i8:249; GISEL: // %bb.0:250; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0251; GISEL-NEXT: umov w8, v0.h[0]252; GISEL-NEXT: umov w9, v0.h[1]253; GISEL-NEXT: umov w10, v0.h[2]254; GISEL-NEXT: umov w11, v0.h[3]255; GISEL-NEXT: orr w8, w8, w9256; GISEL-NEXT: orr w9, w10, w11257; GISEL-NEXT: orr w0, w8, w9258; GISEL-NEXT: ret259 %or_result = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %a)260 ret i8 %or_result261}262 263define i8 @test_redor_v8i8(<8 x i8> %a) {264; CHECK-LABEL: test_redor_v8i8:265; CHECK: // %bb.0:266; CHECK-NEXT: fmov x8, d0267; CHECK-NEXT: orr x8, x8, x8, lsr #32268; CHECK-NEXT: orr x8, x8, x8, lsr #16269; CHECK-NEXT: lsr x9, x8, #8270; CHECK-NEXT: orr w0, w8, w9271; CHECK-NEXT: ret272;273; GISEL-LABEL: test_redor_v8i8:274; GISEL: // %bb.0:275; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0276; GISEL-NEXT: umov w8, v0.b[0]277; GISEL-NEXT: umov w9, v0.b[1]278; GISEL-NEXT: umov w10, v0.b[2]279; GISEL-NEXT: umov w11, v0.b[3]280; GISEL-NEXT: umov w12, v0.b[4]281; GISEL-NEXT: umov w13, v0.b[5]282; GISEL-NEXT: umov w14, v0.b[6]283; GISEL-NEXT: umov w15, v0.b[7]284; GISEL-NEXT: orr w8, w8, w9285; GISEL-NEXT: orr w9, w10, w11286; GISEL-NEXT: orr w10, w12, w13287; GISEL-NEXT: orr w11, w14, w15288; GISEL-NEXT: orr w8, w8, w9289; GISEL-NEXT: orr w9, w10, w11290; GISEL-NEXT: orr w0, w8, w9291; GISEL-NEXT: ret292 %or_result = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a)293 ret i8 %or_result294}295 296define i8 @test_redor_v16i8(<16 x i8> %a) {297; CHECK-LABEL: test_redor_v16i8:298; CHECK: // %bb.0:299; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8300; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b301; CHECK-NEXT: fmov x8, d0302; CHECK-NEXT: orr x8, x8, x8, lsr #32303; CHECK-NEXT: orr x8, x8, x8, lsr #16304; CHECK-NEXT: lsr x9, x8, #8305; CHECK-NEXT: orr w0, w8, w9306; CHECK-NEXT: ret307;308; GISEL-LABEL: test_redor_v16i8:309; GISEL: // %bb.0:310; GISEL-NEXT: mov d1, v0.d[1]311; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b312; GISEL-NEXT: umov w8, v0.b[0]313; GISEL-NEXT: umov w9, v0.b[1]314; GISEL-NEXT: umov w10, v0.b[2]315; GISEL-NEXT: umov w11, v0.b[3]316; GISEL-NEXT: umov w12, v0.b[4]317; GISEL-NEXT: umov w13, v0.b[5]318; GISEL-NEXT: umov w14, v0.b[6]319; GISEL-NEXT: umov w15, v0.b[7]320; GISEL-NEXT: orr w8, w8, w9321; GISEL-NEXT: orr w9, w10, w11322; GISEL-NEXT: orr w10, w12, w13323; GISEL-NEXT: orr w11, w14, w15324; GISEL-NEXT: orr w8, w8, w9325; GISEL-NEXT: orr w9, w10, w11326; GISEL-NEXT: orr w0, w8, w9327; GISEL-NEXT: ret328 %or_result = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a)329 ret i8 %or_result330}331 332define i8 @test_redor_v32i8(<32 x i8> %a) {333; CHECK-LABEL: test_redor_v32i8:334; CHECK: // %bb.0:335; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b336; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8337; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b338; CHECK-NEXT: fmov x8, d0339; CHECK-NEXT: orr x8, x8, x8, lsr #32340; CHECK-NEXT: orr x8, x8, x8, lsr #16341; CHECK-NEXT: lsr x9, x8, #8342; CHECK-NEXT: orr w0, w8, w9343; CHECK-NEXT: ret344;345; GISEL-LABEL: test_redor_v32i8:346; GISEL: // %bb.0:347; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b348; GISEL-NEXT: mov d1, v0.d[1]349; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b350; GISEL-NEXT: umov w8, v0.b[0]351; GISEL-NEXT: umov w9, v0.b[1]352; GISEL-NEXT: umov w10, v0.b[2]353; GISEL-NEXT: umov w11, v0.b[3]354; GISEL-NEXT: umov w12, v0.b[4]355; GISEL-NEXT: umov w13, v0.b[5]356; GISEL-NEXT: umov w14, v0.b[6]357; GISEL-NEXT: umov w15, v0.b[7]358; GISEL-NEXT: orr w8, w8, w9359; GISEL-NEXT: orr w9, w10, w11360; GISEL-NEXT: orr w10, w12, w13361; GISEL-NEXT: orr w11, w14, w15362; GISEL-NEXT: orr w8, w8, w9363; GISEL-NEXT: orr w9, w10, w11364; GISEL-NEXT: orr w0, w8, w9365; GISEL-NEXT: ret366 %or_result = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %a)367 ret i8 %or_result368}369 370define i16 @test_redor_v4i16(<4 x i16> %a) {371; CHECK-LABEL: test_redor_v4i16:372; CHECK: // %bb.0:373; CHECK-NEXT: fmov x8, d0374; CHECK-NEXT: orr x8, x8, x8, lsr #32375; CHECK-NEXT: lsr x9, x8, #16376; CHECK-NEXT: orr w0, w8, w9377; CHECK-NEXT: ret378;379; GISEL-LABEL: test_redor_v4i16:380; GISEL: // %bb.0:381; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0382; GISEL-NEXT: umov w8, v0.h[0]383; GISEL-NEXT: umov w9, v0.h[1]384; GISEL-NEXT: umov w10, v0.h[2]385; GISEL-NEXT: umov w11, v0.h[3]386; GISEL-NEXT: orr w8, w8, w9387; GISEL-NEXT: orr w9, w10, w11388; GISEL-NEXT: orr w0, w8, w9389; GISEL-NEXT: ret390 %or_result = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a)391 ret i16 %or_result392}393 394define i16 @test_redor_v8i16(<8 x i16> %a) {395; CHECK-LABEL: test_redor_v8i16:396; CHECK: // %bb.0:397; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8398; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b399; CHECK-NEXT: fmov x8, d0400; CHECK-NEXT: orr x8, x8, x8, lsr #32401; CHECK-NEXT: lsr x9, x8, #16402; CHECK-NEXT: orr w0, w8, w9403; CHECK-NEXT: ret404;405; GISEL-LABEL: test_redor_v8i16:406; GISEL: // %bb.0:407; GISEL-NEXT: mov d1, v0.d[1]408; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b409; GISEL-NEXT: umov w8, v0.h[0]410; GISEL-NEXT: umov w9, v0.h[1]411; GISEL-NEXT: umov w10, v0.h[2]412; GISEL-NEXT: umov w11, v0.h[3]413; GISEL-NEXT: orr w8, w8, w9414; GISEL-NEXT: orr w9, w10, w11415; GISEL-NEXT: orr w0, w8, w9416; GISEL-NEXT: ret417 %or_result = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a)418 ret i16 %or_result419}420 421define i16 @test_redor_v16i16(<16 x i16> %a) {422; CHECK-LABEL: test_redor_v16i16:423; CHECK: // %bb.0:424; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b425; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8426; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b427; CHECK-NEXT: fmov x8, d0428; CHECK-NEXT: orr x8, x8, x8, lsr #32429; CHECK-NEXT: lsr x9, x8, #16430; CHECK-NEXT: orr w0, w8, w9431; CHECK-NEXT: ret432;433; GISEL-LABEL: test_redor_v16i16:434; GISEL: // %bb.0:435; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b436; GISEL-NEXT: mov d1, v0.d[1]437; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b438; GISEL-NEXT: umov w8, v0.h[0]439; GISEL-NEXT: umov w9, v0.h[1]440; GISEL-NEXT: umov w10, v0.h[2]441; GISEL-NEXT: umov w11, v0.h[3]442; GISEL-NEXT: orr w8, w8, w9443; GISEL-NEXT: orr w9, w10, w11444; GISEL-NEXT: orr w0, w8, w9445; GISEL-NEXT: ret446 %or_result = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %a)447 ret i16 %or_result448}449 450define i32 @test_redor_v2i32(<2 x i32> %a) {451; CHECK-LABEL: test_redor_v2i32:452; CHECK: // %bb.0:453; CHECK-NEXT: fmov x8, d0454; CHECK-NEXT: lsr x9, x8, #32455; CHECK-NEXT: orr w0, w8, w9456; CHECK-NEXT: ret457;458; GISEL-LABEL: test_redor_v2i32:459; GISEL: // %bb.0:460; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0461; GISEL-NEXT: mov w8, v0.s[1]462; GISEL-NEXT: fmov w9, s0463; GISEL-NEXT: orr w0, w9, w8464; GISEL-NEXT: ret465 %or_result = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)466 ret i32 %or_result467}468 469define i32 @test_redor_v4i32(<4 x i32> %a) {470; CHECK-LABEL: test_redor_v4i32:471; CHECK: // %bb.0:472; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8473; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b474; CHECK-NEXT: fmov x8, d0475; CHECK-NEXT: lsr x9, x8, #32476; CHECK-NEXT: orr w0, w8, w9477; CHECK-NEXT: ret478;479; GISEL-LABEL: test_redor_v4i32:480; GISEL: // %bb.0:481; GISEL-NEXT: mov d1, v0.d[1]482; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b483; GISEL-NEXT: mov w8, v0.s[1]484; GISEL-NEXT: fmov w9, s0485; GISEL-NEXT: orr w0, w9, w8486; GISEL-NEXT: ret487 %or_result = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)488 ret i32 %or_result489}490 491define i32 @test_redor_v8i32(<8 x i32> %a) {492; CHECK-LABEL: test_redor_v8i32:493; CHECK: // %bb.0:494; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b495; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8496; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b497; CHECK-NEXT: fmov x8, d0498; CHECK-NEXT: lsr x9, x8, #32499; CHECK-NEXT: orr w0, w8, w9500; CHECK-NEXT: ret501;502; GISEL-LABEL: test_redor_v8i32:503; GISEL: // %bb.0:504; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b505; GISEL-NEXT: mov d1, v0.d[1]506; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b507; GISEL-NEXT: mov w8, v0.s[1]508; GISEL-NEXT: fmov w9, s0509; GISEL-NEXT: orr w0, w9, w8510; GISEL-NEXT: ret511 %or_result = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %a)512 ret i32 %or_result513}514 515define i64 @test_redor_v2i64(<2 x i64> %a) {516; CHECK-LABEL: test_redor_v2i64:517; CHECK: // %bb.0:518; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8519; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b520; CHECK-NEXT: fmov x0, d0521; CHECK-NEXT: ret522;523; GISEL-LABEL: test_redor_v2i64:524; GISEL: // %bb.0:525; GISEL-NEXT: mov x8, v0.d[1]526; GISEL-NEXT: fmov x9, d0527; GISEL-NEXT: orr x0, x9, x8528; GISEL-NEXT: ret529 %or_result = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a)530 ret i64 %or_result531}532 533define i64 @test_redor_v4i64(<4 x i64> %a) {534; CHECK-LABEL: test_redor_v4i64:535; CHECK: // %bb.0:536; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b537; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8538; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b539; CHECK-NEXT: fmov x0, d0540; CHECK-NEXT: ret541;542; GISEL-LABEL: test_redor_v4i64:543; GISEL: // %bb.0:544; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b545; GISEL-NEXT: mov x8, v0.d[1]546; GISEL-NEXT: fmov x9, d0547; GISEL-NEXT: orr x0, x9, x8548; GISEL-NEXT: ret549 %or_result = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %a)550 ret i64 %or_result551}552 553declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)554declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)555declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)556declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)557declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)558declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)559declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)560declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)561declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)562declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)563declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)564declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)565declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)566declare i8 @llvm.vector.reduce.or.v1i8(<1 x i8>)567declare i8 @llvm.vector.reduce.or.v3i8(<3 x i8>)568declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)569declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)570declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)571declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)572