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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+neon | FileCheck %s3; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL4 5define i1 @test_redxor_v1i1(<1 x i1> %a) {6; CHECK-LABEL: test_redxor_v1i1:7; CHECK: // %bb.0:8; CHECK-NEXT: and w0, w0, #0x19; CHECK-NEXT: ret10;11; GISEL-LABEL: test_redxor_v1i1:12; GISEL: // %bb.0:13; GISEL-NEXT: and w0, w0, #0x114; GISEL-NEXT: ret15 %or_result = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> %a)16 ret i1 %or_result17}18 19define i1 @test_redxor_v2i1(<2 x i1> %a) {20; CHECK-LABEL: test_redxor_v2i1:21; CHECK: // %bb.0:22; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s23; CHECK-NEXT: fmov w8, s024; CHECK-NEXT: and w0, w8, #0x125; CHECK-NEXT: ret26;27; GISEL-LABEL: test_redxor_v2i1:28; GISEL: // %bb.0:29; GISEL-NEXT: // kill: def $d0 killed $d0 def $q030; GISEL-NEXT: mov w8, v0.s[1]31; GISEL-NEXT: fmov w9, s032; GISEL-NEXT: eor w8, w9, w833; GISEL-NEXT: and w0, w8, #0x134; GISEL-NEXT: ret35 %or_result = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %a)36 ret i1 %or_result37}38 39define i1 @test_redxor_v4i1(<4 x i1> %a) {40; CHECK-LABEL: test_redxor_v4i1:41; CHECK: // %bb.0:42; CHECK-NEXT: addv h0, v0.4h43; CHECK-NEXT: fmov w8, s044; CHECK-NEXT: and w0, w8, #0x145; CHECK-NEXT: ret46;47; GISEL-LABEL: test_redxor_v4i1:48; GISEL: // %bb.0:49; GISEL-NEXT: // kill: def $d0 killed $d0 def $q050; GISEL-NEXT: umov w8, v0.h[0]51; GISEL-NEXT: umov w9, v0.h[1]52; GISEL-NEXT: umov w10, v0.h[2]53; GISEL-NEXT: umov w11, v0.h[3]54; GISEL-NEXT: eor w8, w8, w955; GISEL-NEXT: eor w9, w10, w1156; GISEL-NEXT: eor w8, w8, w957; GISEL-NEXT: and w0, w8, #0x158; GISEL-NEXT: ret59 %or_result = call i1 @llvm.vector.reduce.xor.v4i1(<4 x i1> %a)60 ret i1 %or_result61}62 63define i1 @test_redxor_v8i1(<8 x i1> %a) {64; CHECK-LABEL: test_redxor_v8i1:65; CHECK: // %bb.0:66; CHECK-NEXT: addv b0, v0.8b67; CHECK-NEXT: fmov w8, s068; CHECK-NEXT: and w0, w8, #0x169; CHECK-NEXT: ret70;71; GISEL-LABEL: test_redxor_v8i1:72; GISEL: // %bb.0:73; GISEL-NEXT: // kill: def $d0 killed $d0 def $q074; GISEL-NEXT: umov w8, v0.b[0]75; GISEL-NEXT: umov w9, v0.b[1]76; GISEL-NEXT: umov w10, v0.b[2]77; GISEL-NEXT: umov w11, v0.b[3]78; GISEL-NEXT: umov w12, v0.b[4]79; GISEL-NEXT: umov w13, v0.b[5]80; GISEL-NEXT: umov w14, v0.b[6]81; GISEL-NEXT: umov w15, v0.b[7]82; GISEL-NEXT: eor w8, w8, w983; GISEL-NEXT: eor w9, w10, w1184; GISEL-NEXT: eor w10, w12, w1385; GISEL-NEXT: eor w11, w14, w1586; GISEL-NEXT: eor w8, w8, w987; GISEL-NEXT: eor w9, w10, w1188; GISEL-NEXT: eor w8, w8, w989; GISEL-NEXT: and w0, w8, #0x190; GISEL-NEXT: ret91 %or_result = call i1 @llvm.vector.reduce.xor.v8i1(<8 x i1> %a)92 ret i1 %or_result93}94 95define i1 @test_redxor_v16i1(<16 x i1> %a) {96; CHECK-LABEL: test_redxor_v16i1:97; CHECK: // %bb.0:98; CHECK-NEXT: addv b0, v0.16b99; CHECK-NEXT: fmov w8, s0100; CHECK-NEXT: and w0, w8, #0x1101; CHECK-NEXT: ret102;103; GISEL-LABEL: test_redxor_v16i1:104; GISEL: // %bb.0:105; GISEL-NEXT: umov w8, v0.b[0]106; GISEL-NEXT: umov w9, v0.b[1]107; GISEL-NEXT: umov w10, v0.b[2]108; GISEL-NEXT: umov w11, v0.b[3]109; GISEL-NEXT: umov w12, v0.b[4]110; GISEL-NEXT: umov w13, v0.b[5]111; GISEL-NEXT: umov w14, v0.b[6]112; GISEL-NEXT: umov w15, v0.b[7]113; GISEL-NEXT: umov w16, v0.b[8]114; GISEL-NEXT: umov w17, v0.b[9]115; GISEL-NEXT: umov w18, v0.b[10]116; GISEL-NEXT: umov w0, v0.b[11]117; GISEL-NEXT: eor w8, w8, w9118; GISEL-NEXT: umov w1, v0.b[12]119; GISEL-NEXT: umov w2, v0.b[13]120; GISEL-NEXT: eor w9, w10, w11121; GISEL-NEXT: eor w10, w12, w13122; GISEL-NEXT: umov w3, v0.b[14]123; GISEL-NEXT: eor w11, w14, w15124; GISEL-NEXT: eor w8, w8, w9125; GISEL-NEXT: umov w4, v0.b[15]126; GISEL-NEXT: eor w12, w16, w17127; GISEL-NEXT: eor w13, w18, w0128; GISEL-NEXT: eor w9, w10, w11129; GISEL-NEXT: eor w14, w1, w2130; GISEL-NEXT: eor w10, w12, w13131; GISEL-NEXT: eor w8, w8, w9132; GISEL-NEXT: eor w15, w3, w4133; GISEL-NEXT: eor w11, w14, w15134; GISEL-NEXT: eor w9, w10, w11135; GISEL-NEXT: eor w8, w8, w9136; GISEL-NEXT: and w0, w8, #0x1137; GISEL-NEXT: ret138 %or_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)139 ret i1 %or_result140}141 142define <16 x i1> @test_redxor_ins_v16i1(<16 x i1> %a) {143; CHECK-LABEL: test_redxor_ins_v16i1:144; CHECK: // %bb.0:145; CHECK-NEXT: addv b0, v0.16b146; CHECK-NEXT: ret147;148; GISEL-LABEL: test_redxor_ins_v16i1:149; GISEL: // %bb.0:150; GISEL-NEXT: umov w8, v0.b[0]151; GISEL-NEXT: umov w9, v0.b[1]152; GISEL-NEXT: umov w10, v0.b[2]153; GISEL-NEXT: umov w11, v0.b[3]154; GISEL-NEXT: umov w12, v0.b[4]155; GISEL-NEXT: umov w13, v0.b[5]156; GISEL-NEXT: umov w14, v0.b[6]157; GISEL-NEXT: umov w15, v0.b[7]158; GISEL-NEXT: umov w16, v0.b[8]159; GISEL-NEXT: umov w17, v0.b[9]160; GISEL-NEXT: umov w18, v0.b[10]161; GISEL-NEXT: umov w0, v0.b[11]162; GISEL-NEXT: eor w8, w8, w9163; GISEL-NEXT: umov w1, v0.b[12]164; GISEL-NEXT: umov w2, v0.b[13]165; GISEL-NEXT: eor w9, w10, w11166; GISEL-NEXT: eor w10, w12, w13167; GISEL-NEXT: umov w3, v0.b[14]168; GISEL-NEXT: eor w11, w14, w15169; GISEL-NEXT: eor w8, w8, w9170; GISEL-NEXT: umov w4, v0.b[15]171; GISEL-NEXT: eor w12, w16, w17172; GISEL-NEXT: eor w13, w18, w0173; GISEL-NEXT: eor w9, w10, w11174; GISEL-NEXT: eor w14, w1, w2175; GISEL-NEXT: eor w10, w12, w13176; GISEL-NEXT: eor w8, w8, w9177; GISEL-NEXT: eor w15, w3, w4178; GISEL-NEXT: eor w11, w14, w15179; GISEL-NEXT: eor w9, w10, w11180; GISEL-NEXT: eor w8, w8, w9181; GISEL-NEXT: fmov s0, w8182; GISEL-NEXT: ret183 %xor_result = call i1 @llvm.vector.reduce.xor.v16i1(<16 x i1> %a)184 %ins = insertelement <16 x i1> poison, i1 %xor_result, i64 0185 ret <16 x i1> %ins186}187 188define i8 @test_redxor_v1i8(<1 x i8> %a) {189; CHECK-LABEL: test_redxor_v1i8:190; CHECK: // %bb.0:191; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0192; CHECK-NEXT: umov w0, v0.b[0]193; CHECK-NEXT: ret194;195; GISEL-LABEL: test_redxor_v1i8:196; GISEL: // %bb.0:197; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0198; GISEL-NEXT: umov w0, v0.b[0]199; GISEL-NEXT: ret200 %xor_result = call i8 @llvm.vector.reduce.xor.v1i8(<1 x i8> %a)201 ret i8 %xor_result202}203 204define i8 @test_redxor_v3i8(<3 x i8> %a) {205; CHECK-LABEL: test_redxor_v3i8:206; CHECK: // %bb.0:207; CHECK-NEXT: movi v0.2d, #0000000000000000208; CHECK-NEXT: mov v0.h[0], w0209; CHECK-NEXT: mov v0.h[1], w1210; CHECK-NEXT: fmov x8, d0211; CHECK-NEXT: mov v0.h[2], w2212; CHECK-NEXT: fmov x9, d0213; CHECK-NEXT: lsr x10, x9, #32214; CHECK-NEXT: lsr x9, x9, #16215; CHECK-NEXT: eor w8, w8, w10216; CHECK-NEXT: eor w0, w8, w9217; CHECK-NEXT: ret218;219; GISEL-LABEL: test_redxor_v3i8:220; GISEL: // %bb.0:221; GISEL-NEXT: eor w8, w0, w1222; GISEL-NEXT: eor w0, w8, w2223; GISEL-NEXT: ret224 %xor_result = call i8 @llvm.vector.reduce.xor.v3i8(<3 x i8> %a)225 ret i8 %xor_result226}227 228define i8 @test_redxor_v4i8(<4 x i8> %a) {229; CHECK-LABEL: test_redxor_v4i8:230; CHECK: // %bb.0:231; CHECK-NEXT: fmov x8, d0232; CHECK-NEXT: eor x8, x8, x8, lsr #32233; CHECK-NEXT: lsr x9, x8, #16234; CHECK-NEXT: eor w0, w8, w9235; CHECK-NEXT: ret236;237; GISEL-LABEL: test_redxor_v4i8:238; GISEL: // %bb.0:239; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0240; GISEL-NEXT: umov w8, v0.h[0]241; GISEL-NEXT: umov w9, v0.h[1]242; GISEL-NEXT: umov w10, v0.h[2]243; GISEL-NEXT: umov w11, v0.h[3]244; GISEL-NEXT: eor w8, w8, w9245; GISEL-NEXT: eor w9, w10, w11246; GISEL-NEXT: eor w0, w8, w9247; GISEL-NEXT: ret248 %xor_result = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %a)249 ret i8 %xor_result250}251 252define i8 @test_redxor_v8i8(<8 x i8> %a) {253; CHECK-LABEL: test_redxor_v8i8:254; CHECK: // %bb.0:255; CHECK-NEXT: fmov x8, d0256; CHECK-NEXT: eor x8, x8, x8, lsr #32257; CHECK-NEXT: eor x8, x8, x8, lsr #16258; CHECK-NEXT: lsr x9, x8, #8259; CHECK-NEXT: eor w0, w8, w9260; CHECK-NEXT: ret261;262; GISEL-LABEL: test_redxor_v8i8:263; GISEL: // %bb.0:264; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0265; GISEL-NEXT: umov w8, v0.b[0]266; GISEL-NEXT: umov w9, v0.b[1]267; GISEL-NEXT: umov w10, v0.b[2]268; GISEL-NEXT: umov w11, v0.b[3]269; GISEL-NEXT: umov w12, v0.b[4]270; GISEL-NEXT: umov w13, v0.b[5]271; GISEL-NEXT: umov w14, v0.b[6]272; GISEL-NEXT: umov w15, v0.b[7]273; GISEL-NEXT: eor w8, w8, w9274; GISEL-NEXT: eor w9, w10, w11275; GISEL-NEXT: eor w10, w12, w13276; GISEL-NEXT: eor w11, w14, w15277; GISEL-NEXT: eor w8, w8, w9278; GISEL-NEXT: eor w9, w10, w11279; GISEL-NEXT: eor w0, w8, w9280; GISEL-NEXT: ret281 %xor_result = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %a)282 ret i8 %xor_result283}284 285define i8 @test_redxor_v16i8(<16 x i8> %a) {286; CHECK-LABEL: test_redxor_v16i8:287; CHECK: // %bb.0:288; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8289; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b290; CHECK-NEXT: fmov x8, d0291; CHECK-NEXT: eor x8, x8, x8, lsr #32292; CHECK-NEXT: eor x8, x8, x8, lsr #16293; CHECK-NEXT: lsr x9, x8, #8294; CHECK-NEXT: eor w0, w8, w9295; CHECK-NEXT: ret296;297; GISEL-LABEL: test_redxor_v16i8:298; GISEL: // %bb.0:299; GISEL-NEXT: mov d1, v0.d[1]300; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b301; GISEL-NEXT: umov w8, v0.b[0]302; GISEL-NEXT: umov w9, v0.b[1]303; GISEL-NEXT: umov w10, v0.b[2]304; GISEL-NEXT: umov w11, v0.b[3]305; GISEL-NEXT: umov w12, v0.b[4]306; GISEL-NEXT: umov w13, v0.b[5]307; GISEL-NEXT: umov w14, v0.b[6]308; GISEL-NEXT: umov w15, v0.b[7]309; GISEL-NEXT: eor w8, w8, w9310; GISEL-NEXT: eor w9, w10, w11311; GISEL-NEXT: eor w10, w12, w13312; GISEL-NEXT: eor w11, w14, w15313; GISEL-NEXT: eor w8, w8, w9314; GISEL-NEXT: eor w9, w10, w11315; GISEL-NEXT: eor w0, w8, w9316; GISEL-NEXT: ret317 %xor_result = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %a)318 ret i8 %xor_result319}320 321define i8 @test_redxor_v32i8(<32 x i8> %a) {322; CHECK-LABEL: test_redxor_v32i8:323; CHECK: // %bb.0:324; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b325; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8326; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b327; CHECK-NEXT: fmov x8, d0328; CHECK-NEXT: eor x8, x8, x8, lsr #32329; CHECK-NEXT: eor x8, x8, x8, lsr #16330; CHECK-NEXT: lsr x9, x8, #8331; CHECK-NEXT: eor w0, w8, w9332; CHECK-NEXT: ret333;334; GISEL-LABEL: test_redxor_v32i8:335; GISEL: // %bb.0:336; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b337; GISEL-NEXT: mov d1, v0.d[1]338; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b339; GISEL-NEXT: umov w8, v0.b[0]340; GISEL-NEXT: umov w9, v0.b[1]341; GISEL-NEXT: umov w10, v0.b[2]342; GISEL-NEXT: umov w11, v0.b[3]343; GISEL-NEXT: umov w12, v0.b[4]344; GISEL-NEXT: umov w13, v0.b[5]345; GISEL-NEXT: umov w14, v0.b[6]346; GISEL-NEXT: umov w15, v0.b[7]347; GISEL-NEXT: eor w8, w8, w9348; GISEL-NEXT: eor w9, w10, w11349; GISEL-NEXT: eor w10, w12, w13350; GISEL-NEXT: eor w11, w14, w15351; GISEL-NEXT: eor w8, w8, w9352; GISEL-NEXT: eor w9, w10, w11353; GISEL-NEXT: eor w0, w8, w9354; GISEL-NEXT: ret355 %xor_result = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %a)356 ret i8 %xor_result357}358 359define i16 @test_redxor_v4i16(<4 x i16> %a) {360; CHECK-LABEL: test_redxor_v4i16:361; CHECK: // %bb.0:362; CHECK-NEXT: fmov x8, d0363; CHECK-NEXT: eor x8, x8, x8, lsr #32364; CHECK-NEXT: lsr x9, x8, #16365; CHECK-NEXT: eor w0, w8, w9366; CHECK-NEXT: ret367;368; GISEL-LABEL: test_redxor_v4i16:369; GISEL: // %bb.0:370; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0371; GISEL-NEXT: umov w8, v0.h[0]372; GISEL-NEXT: umov w9, v0.h[1]373; GISEL-NEXT: umov w10, v0.h[2]374; GISEL-NEXT: umov w11, v0.h[3]375; GISEL-NEXT: eor w8, w8, w9376; GISEL-NEXT: eor w9, w10, w11377; GISEL-NEXT: eor w0, w8, w9378; GISEL-NEXT: ret379 %xor_result = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %a)380 ret i16 %xor_result381}382 383define i16 @test_redxor_v8i16(<8 x i16> %a) {384; CHECK-LABEL: test_redxor_v8i16:385; CHECK: // %bb.0:386; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8387; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b388; CHECK-NEXT: fmov x8, d0389; CHECK-NEXT: eor x8, x8, x8, lsr #32390; CHECK-NEXT: lsr x9, x8, #16391; CHECK-NEXT: eor w0, w8, w9392; CHECK-NEXT: ret393;394; GISEL-LABEL: test_redxor_v8i16:395; GISEL: // %bb.0:396; GISEL-NEXT: mov d1, v0.d[1]397; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b398; GISEL-NEXT: umov w8, v0.h[0]399; GISEL-NEXT: umov w9, v0.h[1]400; GISEL-NEXT: umov w10, v0.h[2]401; GISEL-NEXT: umov w11, v0.h[3]402; GISEL-NEXT: eor w8, w8, w9403; GISEL-NEXT: eor w9, w10, w11404; GISEL-NEXT: eor w0, w8, w9405; GISEL-NEXT: ret406 %xor_result = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %a)407 ret i16 %xor_result408}409 410define i16 @test_redxor_v16i16(<16 x i16> %a) {411; CHECK-LABEL: test_redxor_v16i16:412; CHECK: // %bb.0:413; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b414; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8415; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b416; CHECK-NEXT: fmov x8, d0417; CHECK-NEXT: eor x8, x8, x8, lsr #32418; CHECK-NEXT: lsr x9, x8, #16419; CHECK-NEXT: eor w0, w8, w9420; CHECK-NEXT: ret421;422; GISEL-LABEL: test_redxor_v16i16:423; GISEL: // %bb.0:424; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b425; GISEL-NEXT: mov d1, v0.d[1]426; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b427; GISEL-NEXT: umov w8, v0.h[0]428; GISEL-NEXT: umov w9, v0.h[1]429; GISEL-NEXT: umov w10, v0.h[2]430; GISEL-NEXT: umov w11, v0.h[3]431; GISEL-NEXT: eor w8, w8, w9432; GISEL-NEXT: eor w9, w10, w11433; GISEL-NEXT: eor w0, w8, w9434; GISEL-NEXT: ret435 %xor_result = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %a)436 ret i16 %xor_result437}438 439define i32 @test_redxor_v2i32(<2 x i32> %a) {440; CHECK-LABEL: test_redxor_v2i32:441; CHECK: // %bb.0:442; CHECK-NEXT: fmov x8, d0443; CHECK-NEXT: lsr x9, x8, #32444; CHECK-NEXT: eor w0, w8, w9445; CHECK-NEXT: ret446;447; GISEL-LABEL: test_redxor_v2i32:448; GISEL: // %bb.0:449; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0450; GISEL-NEXT: mov w8, v0.s[1]451; GISEL-NEXT: fmov w9, s0452; GISEL-NEXT: eor w0, w9, w8453; GISEL-NEXT: ret454 %xor_result = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a)455 ret i32 %xor_result456}457 458define i32 @test_redxor_v4i32(<4 x i32> %a) {459; CHECK-LABEL: test_redxor_v4i32:460; CHECK: // %bb.0:461; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8462; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b463; CHECK-NEXT: fmov x8, d0464; CHECK-NEXT: lsr x9, x8, #32465; CHECK-NEXT: eor w0, w8, w9466; CHECK-NEXT: ret467;468; GISEL-LABEL: test_redxor_v4i32:469; GISEL: // %bb.0:470; GISEL-NEXT: mov d1, v0.d[1]471; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b472; GISEL-NEXT: mov w8, v0.s[1]473; GISEL-NEXT: fmov w9, s0474; GISEL-NEXT: eor w0, w9, w8475; GISEL-NEXT: ret476 %xor_result = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)477 ret i32 %xor_result478}479 480define i32 @test_redxor_v8i32(<8 x i32> %a) {481; CHECK-LABEL: test_redxor_v8i32:482; CHECK: // %bb.0:483; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b484; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8485; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b486; CHECK-NEXT: fmov x8, d0487; CHECK-NEXT: lsr x9, x8, #32488; CHECK-NEXT: eor w0, w8, w9489; CHECK-NEXT: ret490;491; GISEL-LABEL: test_redxor_v8i32:492; GISEL: // %bb.0:493; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b494; GISEL-NEXT: mov d1, v0.d[1]495; GISEL-NEXT: eor v0.8b, v0.8b, v1.8b496; GISEL-NEXT: mov w8, v0.s[1]497; GISEL-NEXT: fmov w9, s0498; GISEL-NEXT: eor w0, w9, w8499; GISEL-NEXT: ret500 %xor_result = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %a)501 ret i32 %xor_result502}503 504define i64 @test_redxor_v2i64(<2 x i64> %a) {505; CHECK-LABEL: test_redxor_v2i64:506; CHECK: // %bb.0:507; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8508; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b509; CHECK-NEXT: fmov x0, d0510; CHECK-NEXT: ret511;512; GISEL-LABEL: test_redxor_v2i64:513; GISEL: // %bb.0:514; GISEL-NEXT: mov x8, v0.d[1]515; GISEL-NEXT: fmov x9, d0516; GISEL-NEXT: eor x0, x9, x8517; GISEL-NEXT: ret518 %xor_result = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %a)519 ret i64 %xor_result520}521 522define i64 @test_redxor_v4i64(<4 x i64> %a) {523; CHECK-LABEL: test_redxor_v4i64:524; CHECK: // %bb.0:525; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b526; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8527; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b528; CHECK-NEXT: fmov x0, d0529; CHECK-NEXT: ret530;531; GISEL-LABEL: test_redxor_v4i64:532; GISEL: // %bb.0:533; GISEL-NEXT: eor v0.16b, v0.16b, v1.16b534; GISEL-NEXT: mov x8, v0.d[1]535; GISEL-NEXT: fmov x9, d0536; GISEL-NEXT: eor x0, x9, x8537; GISEL-NEXT: ret538 %xor_result = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %a)539 ret i64 %xor_result540}541 542declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)543declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)544declare i1 @llvm.vector.reduce.xor.v4i1(<4 x i1>)545declare i1 @llvm.vector.reduce.xor.v8i1(<8 x i1>)546declare i1 @llvm.vector.reduce.xor.v16i1(<16 x i1>)547declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)548declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)549declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)550declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)551declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)552declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)553declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)554declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)555declare i8 @llvm.vector.reduce.xor.v1i8(<1 x i8>)556declare i8 @llvm.vector.reduce.xor.v3i8(<3 x i8>)557declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)558declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)559declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)560declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)561