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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -frame-pointer=all -o - %s | FileCheck %s3 4; When generating DAG selection tables, TableGen used to only flag an5; instruction as needing a chain on its own account if it had a built-in pattern6; which used the chain. This meant that the AArch64 load/stores weren't7; recognised and so both loads from %locvar below were coalesced into a single8; LS8_LDR instruction (same operands other than the non-existent chain) and the9; increment was lost at return.10 11; This was obviously a Bad Thing.12 13declare void @bar(ptr)14 15define i64 @test_chains() {16; CHECK-LABEL: test_chains:17; CHECK: ; %bb.0:18; CHECK-NEXT: sub sp, sp, #3219; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill20; CHECK-NEXT: add x29, sp, #1621; CHECK-NEXT: .cfi_def_cfa w29, 1622; CHECK-NEXT: .cfi_offset w30, -823; CHECK-NEXT: .cfi_offset w29, -1624; CHECK-NEXT: sub x0, x29, #125; CHECK-NEXT: bl _bar26; CHECK-NEXT: ldurb w8, [x29, #-1]27; CHECK-NEXT: add x8, x8, #128; CHECK-NEXT: sturb w8, [x29, #-1]29; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload30; CHECK-NEXT: and x0, x8, #0xff31; CHECK-NEXT: add sp, sp, #3232; CHECK-NEXT: ret33 34 %locvar = alloca i835 36 call void @bar(ptr %locvar)37 38 %inc.1 = load i8, ptr %locvar39 %inc.2 = zext i8 %inc.1 to i6440 %inc.3 = add i64 %inc.2, 141 %inc.4 = trunc i64 %inc.3 to i842 store i8 %inc.4, ptr %locvar43 44 45 %ret.1 = load i8, ptr %locvar46 %ret.2 = zext i8 %ret.1 to i6447 ret i64 %ret.248}49