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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s3 4;; This used to cause a backend crash about not being able to5;; select ROTL. Make sure if generates the basic ushr/shl.6define <2 x i64> @testcase(ptr %in) {7; CHECK-LABEL: testcase:8; CHECK: // %bb.0:9; CHECK-NEXT: ldr q1, [x0]10; CHECK-NEXT: shl v0.2d, v1.2d, #5611; CHECK-NEXT: usra v0.2d, v1.2d, #812; CHECK-NEXT: ret13 %1 = load <2 x i64>, ptr %in14 %2 = lshr <2 x i64> %1, <i64 8, i64 8>15 %3 = shl <2 x i64> %1, <i64 56, i64 56>16 %4 = or <2 x i64> %2, %317 ret <2 x i64> %418}19 20;; This used to cause a miscompile because rot combine21;; doesn't handle negative shift well.22define i5 @pr59898(i5 %x) {23; CHECK-LABEL: pr59898:24; CHECK: // %bb.0:25; CHECK-NEXT: ubfx w8, w0, #1, #426; CHECK-NEXT: orr w0, w8, w0, lsl #427; CHECK-NEXT: ret28 %r1 = call i5 @llvm.fshr.i5(i5 %x, i5 %x, i5 3)29 %r2 = call i5 @llvm.fshl.i5(i5 %r1, i5 %r1, i5 2)30 ret i5 %r231}32 33declare i5 @llvm.fshl.i5(i5, i5, i5)34declare i5 @llvm.fshr.i5(i5, i5, i5)35