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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version -52; RUN: llc %s -mtriple=aarch64 -o - | FileCheck %s3 4define <4 x i16> @NarrowAShrI32By5(<4 x i32> %x) {5; CHECK-LABEL: NarrowAShrI32By5:6; CHECK: // %bb.0:7; CHECK-NEXT: sqrshrn v0.4h, v0.4s, #58; CHECK-NEXT: ret9 %s = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)10 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)11 ret <4 x i16> %r12}13 14define <4 x i16> @NarrowAShrU32By5(<4 x i32> %x) {15; CHECK-LABEL: NarrowAShrU32By5:16; CHECK: // %bb.0:17; CHECK-NEXT: srshr v0.4s, v0.4s, #518; CHECK-NEXT: uqxtn v0.4h, v0.4s19; CHECK-NEXT: ret20 %s = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)21 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)22 ret <4 x i16> %r23}24 25define <4 x i16> @NarrowAShrI32By5ToU16(<4 x i32> %x) {26; CHECK-LABEL: NarrowAShrI32By5ToU16:27; CHECK: // %bb.0:28; CHECK-NEXT: sqrshrun v0.4h, v0.4s, #529; CHECK-NEXT: ret30 %s = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)31 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)32 ret <4 x i16> %r33}34 35define <4 x i16> @NarrowLShrI32By5(<4 x i32> %x) {36; CHECK-LABEL: NarrowLShrI32By5:37; CHECK: // %bb.0:38; CHECK-NEXT: urshr v0.4s, v0.4s, #539; CHECK-NEXT: sqxtn v0.4h, v0.4s40; CHECK-NEXT: ret41 %s = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)42 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)43 ret <4 x i16> %r44}45 46define <4 x i16> @NarrowLShrU32By5(<4 x i32> %x) {47; CHECK-LABEL: NarrowLShrU32By5:48; CHECK: // %bb.0:49; CHECK-NEXT: uqrshrn v0.4h, v0.4s, #550; CHECK-NEXT: ret51 %s = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)52 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)53 ret <4 x i16> %r54}55 56define <4 x i16> @NarrowLShrI32By5ToU16(<4 x i32> %x) {57; CHECK-LABEL: NarrowLShrI32By5ToU16:58; CHECK: // %bb.0:59; CHECK-NEXT: urshr v0.4s, v0.4s, #560; CHECK-NEXT: sqxtun v0.4h, v0.4s61; CHECK-NEXT: ret62 %s = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)63 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)64 ret <4 x i16> %r65}66 67 68define <2 x i32> @NarrowAShri64By5(<2 x i64> %x) {69; CHECK-LABEL: NarrowAShri64By5:70; CHECK: // %bb.0:71; CHECK-NEXT: sqrshrn v0.2s, v0.2d, #572; CHECK-NEXT: ret73 %s = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)74 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %s)75 ret <2 x i32> %r76}77 78define <2 x i32> @NarrowAShrU64By5(<2 x i64> %x) {79; CHECK-LABEL: NarrowAShrU64By5:80; CHECK: // %bb.0:81; CHECK-NEXT: srshr v0.2d, v0.2d, #582; CHECK-NEXT: uqxtn v0.2s, v0.2d83; CHECK-NEXT: ret84 %s = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)85 %r = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %s)86 ret <2 x i32> %r87}88 89define <2 x i32> @NarrowAShri64By5ToU32(<2 x i64> %x) {90; CHECK-LABEL: NarrowAShri64By5ToU32:91; CHECK: // %bb.0:92; CHECK-NEXT: sqrshrun v0.2s, v0.2d, #593; CHECK-NEXT: ret94 %s = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)95 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %s)96 ret <2 x i32> %r97}98 99define <2 x i32> @NarrowLShri64By5(<2 x i64> %x) {100; CHECK-LABEL: NarrowLShri64By5:101; CHECK: // %bb.0:102; CHECK-NEXT: urshr v0.2d, v0.2d, #5103; CHECK-NEXT: sqxtn v0.2s, v0.2d104; CHECK-NEXT: ret105 %s = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)106 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %s)107 ret <2 x i32> %r108}109 110define <2 x i32> @NarrowLShrU64By5(<2 x i64> %x) {111; CHECK-LABEL: NarrowLShrU64By5:112; CHECK: // %bb.0:113; CHECK-NEXT: uqrshrn v0.2s, v0.2d, #5114; CHECK-NEXT: ret115 %s = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)116 %r = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %s)117 ret <2 x i32> %r118}119 120define <2 x i32> @NarrowLShri64By5ToU32(<2 x i64> %x) {121; CHECK-LABEL: NarrowLShri64By5ToU32:122; CHECK: // %bb.0:123; CHECK-NEXT: urshr v0.2d, v0.2d, #5124; CHECK-NEXT: sqxtun v0.2s, v0.2d125; CHECK-NEXT: ret126 %s = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)127 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %s)128 ret <2 x i32> %r129}130 131 132define <8 x i8> @NarrowAShri16By5(<8 x i16> %x) {133; CHECK-LABEL: NarrowAShri16By5:134; CHECK: // %bb.0:135; CHECK-NEXT: sqrshrn v0.8b, v0.8h, #5136; CHECK-NEXT: ret137 %s = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)138 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %s)139 ret <8 x i8> %r140}141 142define <8 x i8> @NarrowAShrU16By5(<8 x i16> %x) {143; CHECK-LABEL: NarrowAShrU16By5:144; CHECK: // %bb.0:145; CHECK-NEXT: srshr v0.8h, v0.8h, #5146; CHECK-NEXT: uqxtn v0.8b, v0.8h147; CHECK-NEXT: ret148 %s = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)149 %r = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %s)150 ret <8 x i8> %r151}152 153define <8 x i8> @NarrowAShri16By5ToU8(<8 x i16> %x) {154; CHECK-LABEL: NarrowAShri16By5ToU8:155; CHECK: // %bb.0:156; CHECK-NEXT: sqrshrun v0.8b, v0.8h, #5157; CHECK-NEXT: ret158 %s = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)159 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %s)160 ret <8 x i8> %r161}162 163define <8 x i8> @NarrowLShri16By5(<8 x i16> %x) {164; CHECK-LABEL: NarrowLShri16By5:165; CHECK: // %bb.0:166; CHECK-NEXT: urshr v0.8h, v0.8h, #5167; CHECK-NEXT: sqxtn v0.8b, v0.8h168; CHECK-NEXT: ret169 %s = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)170 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %s)171 ret <8 x i8> %r172}173 174define <8 x i8> @NarrowLShrU16By5(<8 x i16> %x) {175; CHECK-LABEL: NarrowLShrU16By5:176; CHECK: // %bb.0:177; CHECK-NEXT: uqrshrn v0.8b, v0.8h, #5178; CHECK-NEXT: ret179 %s = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)180 %r = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %s)181 ret <8 x i8> %r182}183 184define <8 x i8> @NarrowLShri16By5ToU8(<8 x i16> %x) {185; CHECK-LABEL: NarrowLShri16By5ToU8:186; CHECK: // %bb.0:187; CHECK-NEXT: urshr v0.8h, v0.8h, #5188; CHECK-NEXT: sqxtun v0.8b, v0.8h189; CHECK-NEXT: ret190 %s = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)191 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %s)192 ret <8 x i8> %r193}194 195 196 197 198 199define <4 x i16> @NarrowAShrI32By31(<4 x i32> %x) {200; CHECK-LABEL: NarrowAShrI32By31:201; CHECK: // %bb.0:202; CHECK-NEXT: sqrshrn v0.4h, v0.4s, #16203; CHECK-NEXT: ret204 %s = call <4 x i32> @llvm.aarch64.neon.srshl(<4 x i32> %x, <4 x i32> <i32 -16, i32 -16, i32 -16, i32 -16>)205 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)206 ret <4 x i16> %r207}208 209define <4 x i16> @NarrowAShrI32By31ToU16(<4 x i32> %x) {210; CHECK-LABEL: NarrowAShrI32By31ToU16:211; CHECK: // %bb.0:212; CHECK-NEXT: sqrshrun v0.4h, v0.4s, #16213; CHECK-NEXT: ret214 %s = call <4 x i32> @llvm.aarch64.neon.srshl(<4 x i32> %x, <4 x i32> <i32 -16, i32 -16, i32 -16, i32 -16>)215 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)216 ret <4 x i16> %r217}218 219define <4 x i16> @NarrowLShrU32By31(<4 x i32> %x) {220; CHECK-LABEL: NarrowLShrU32By31:221; CHECK: // %bb.0:222; CHECK-NEXT: uqrshrn v0.4h, v0.4s, #16223; CHECK-NEXT: ret224 %s = call <4 x i32> @llvm.aarch64.neon.urshl(<4 x i32> %x, <4 x i32> <i32 -16, i32 -16, i32 -16, i32 -16>)225 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)226 ret <4 x i16> %r227}228 229 230define <16 x i8> @signed_minmax_v8i16_to_v16i8(<8 x i16> %x, <8 x i16> %y) {231; CHECK-LABEL: signed_minmax_v8i16_to_v16i8:232; CHECK: // %bb.0: // %entry233; CHECK-NEXT: sqrshrn v0.8b, v0.8h, #5234; CHECK-NEXT: sqrshrn2 v0.16b, v1.8h, #5235; CHECK-NEXT: ret236entry:237 %l = call <8 x i16> @llvm.aarch64.neon.srshl(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)238 %h = call <8 x i16> @llvm.aarch64.neon.srshl(<8 x i16> %y, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)239 %s = shufflevector <8 x i16> %l, <8 x i16> %h, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>240 %min = call <16 x i16> @llvm.smin.v8i16(<16 x i16> %s, <16 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)241 %max = call <16 x i16> @llvm.smax.v8i16(<16 x i16> %min, <16 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)242 %trunc = trunc <16 x i16> %max to <16 x i8>243 ret <16 x i8> %trunc244}245 246define <16 x i8> @unsigned_minmax_v8i16_to_v16i8(<8 x i16> %x, <8 x i16> %y) {247; CHECK-LABEL: unsigned_minmax_v8i16_to_v16i8:248; CHECK: // %bb.0: // %entry249; CHECK-NEXT: uqrshrn v0.8b, v0.8h, #5250; CHECK-NEXT: uqrshrn2 v0.16b, v1.8h, #5251; CHECK-NEXT: ret252entry:253 %l = call <8 x i16> @llvm.aarch64.neon.urshl(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)254 %h = call <8 x i16> @llvm.aarch64.neon.urshl(<8 x i16> %y, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)255 %s = shufflevector <8 x i16> %l, <8 x i16> %h, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>256 %min = call <16 x i16> @llvm.umin.v8i16(<16 x i16> %s, <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)257 %trunc = trunc <16 x i16> %min to <16 x i8>258 ret <16 x i8> %trunc259}260 261define <16 x i8> @unsigned_signed_minmax_v8i16_to_v16i8(<8 x i16> %x, <8 x i16> %y) {262; CHECK-LABEL: unsigned_signed_minmax_v8i16_to_v16i8:263; CHECK: // %bb.0: // %entry264; CHECK-NEXT: sqrshrun v0.8b, v0.8h, #5265; CHECK-NEXT: sqrshrun2 v0.16b, v1.8h, #5266; CHECK-NEXT: ret267entry:268 %l = call <8 x i16> @llvm.aarch64.neon.srshl(<8 x i16> %x, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)269 %h = call <8 x i16> @llvm.aarch64.neon.srshl(<8 x i16> %y, <8 x i16> <i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5, i16 -5>)270 %s = shufflevector <8 x i16> %l, <8 x i16> %h, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>271 %max = call <16 x i16> @llvm.smax.v8i16(<16 x i16> %s, <16 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)272 %min = call <16 x i16> @llvm.umin.v8i16(<16 x i16> %max, <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)273 %trunc = trunc <16 x i16> %min to <16 x i8>274 ret <16 x i8> %trunc275}276 277 278define <8 x i16> @signed_minmax_v4i32_to_v8i16(<4 x i32> %x, <4 x i32> %y) {279; CHECK-LABEL: signed_minmax_v4i32_to_v8i16:280; CHECK: // %bb.0: // %entry281; CHECK-NEXT: sqrshrn v0.4h, v0.4s, #5282; CHECK-NEXT: sqrshrn2 v0.8h, v1.4s, #5283; CHECK-NEXT: ret284entry:285 %l = call <4 x i32> @llvm.aarch64.neon.srshl(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)286 %h = call <4 x i32> @llvm.aarch64.neon.srshl(<4 x i32> %y, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)287 %s = shufflevector <4 x i32> %l, <4 x i32> %h, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>288 %min = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %s, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)289 %max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %min, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)290 %trunc = trunc <8 x i32> %max to <8 x i16>291 ret <8 x i16> %trunc292}293 294define <8 x i16> @unsigned_minmax_v4i32_to_v8i16(<4 x i32> %x, <4 x i32> %y) {295; CHECK-LABEL: unsigned_minmax_v4i32_to_v8i16:296; CHECK: // %bb.0: // %entry297; CHECK-NEXT: uqrshrn v0.4h, v0.4s, #5298; CHECK-NEXT: uqrshrn2 v0.8h, v1.4s, #5299; CHECK-NEXT: ret300entry:301 %l = call <4 x i32> @llvm.aarch64.neon.urshl(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)302 %h = call <4 x i32> @llvm.aarch64.neon.urshl(<4 x i32> %y, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)303 %s = shufflevector <4 x i32> %l, <4 x i32> %h, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>304 %min = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %s, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)305 %trunc = trunc <8 x i32> %min to <8 x i16>306 ret <8 x i16> %trunc307}308 309define <8 x i16> @unsigned_signed_minmax_v4i32_to_v8i16(<4 x i32> %x, <4 x i32> %y) {310; CHECK-LABEL: unsigned_signed_minmax_v4i32_to_v8i16:311; CHECK: // %bb.0: // %entry312; CHECK-NEXT: sqrshrun v0.4h, v0.4s, #5313; CHECK-NEXT: sqrshrun2 v0.8h, v1.4s, #5314; CHECK-NEXT: ret315entry:316 %l = call <4 x i32> @llvm.aarch64.neon.srshl(<4 x i32> %x, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)317 %h = call <4 x i32> @llvm.aarch64.neon.srshl(<4 x i32> %y, <4 x i32> <i32 -5, i32 -5, i32 -5, i32 -5>)318 %s = shufflevector <4 x i32> %l, <4 x i32> %h, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>319 %max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %s, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>)320 %min = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %max, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)321 %trunc = trunc <8 x i32> %min to <8 x i16>322 ret <8 x i16> %trunc323}324 325 326define <4 x i32> @signed_minmax_v4i64_to_v8i32(<2 x i64> %x, <2 x i64> %y) {327; CHECK-LABEL: signed_minmax_v4i64_to_v8i32:328; CHECK: // %bb.0: // %entry329; CHECK-NEXT: sqrshrn v0.2s, v0.2d, #5330; CHECK-NEXT: sqrshrn2 v0.4s, v1.2d, #5331; CHECK-NEXT: ret332entry:333 %l = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)334 %h = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %y, <2 x i64> <i64 -5, i64 -5>)335 %s = shufflevector <2 x i64> %l, <2 x i64> %h, <4 x i32> <i32 0, i32 1, i32 2, i32 3>336 %min = call <4 x i64> @llvm.smin.v8i64(<4 x i64> %s, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)337 %max = call <4 x i64> @llvm.smax.v8i64(<4 x i64> %min, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)338 %trunc = trunc <4 x i64> %max to <4 x i32>339 ret <4 x i32> %trunc340}341 342define <4 x i32> @unsigned_minmax_v4i64_to_v8i32(<2 x i64> %x, <2 x i64> %y) {343; CHECK-LABEL: unsigned_minmax_v4i64_to_v8i32:344; CHECK: // %bb.0: // %entry345; CHECK-NEXT: uqrshrn v0.2s, v0.2d, #5346; CHECK-NEXT: uqrshrn2 v0.4s, v1.2d, #5347; CHECK-NEXT: ret348entry:349 %l = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)350 %h = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %y, <2 x i64> <i64 -5, i64 -5>)351 %s = shufflevector <2 x i64> %l, <2 x i64> %h, <4 x i32> <i32 0, i32 1, i32 2, i32 3>352 %min = call <4 x i64> @llvm.umin.v8i64(<4 x i64> %s, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)353 %trunc = trunc <4 x i64> %min to <4 x i32>354 ret <4 x i32> %trunc355}356 357define <4 x i32> @unsigned_signed_minmax_v4i64_to_v8i32(<2 x i64> %x, <2 x i64> %y) {358; CHECK-LABEL: unsigned_signed_minmax_v4i64_to_v8i32:359; CHECK: // %bb.0: // %entry360; CHECK-NEXT: sqrshrun v0.2s, v0.2d, #5361; CHECK-NEXT: sqrshrun2 v0.4s, v1.2d, #5362; CHECK-NEXT: ret363entry:364 %l = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %x, <2 x i64> <i64 -5, i64 -5>)365 %h = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %y, <2 x i64> <i64 -5, i64 -5>)366 %s = shufflevector <2 x i64> %l, <2 x i64> %h, <4 x i32> <i32 0, i32 1, i32 2, i32 3>367 %max = call <4 x i64> @llvm.smax.v8i64(<4 x i64> %s, <4 x i64> <i64 0, i64 0, i64 0, i64 0>)368 %min = call <4 x i64> @llvm.umin.v8i64(<4 x i64> %max, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)369 %trunc = trunc <4 x i64> %min to <4 x i32>370 ret <4 x i32> %trunc371}372