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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-none-elf < %s | FileCheck %s3 4 5define <2 x i16> @saturating_2xi16(<2 x i16> %a, <2 x i16> %b) {6; CHECK-LABEL: saturating_2xi16:7; CHECK: // %bb.0:8; CHECK-NEXT: shl v0.2s, v0.2s, #169; CHECK-NEXT: shl v1.2s, v1.2s, #1610; CHECK-NEXT: sshr v0.2s, v0.2s, #1611; CHECK-NEXT: sshr v1.2s, v1.2s, #1612; CHECK-NEXT: sqdmulh v0.2s, v1.2s, v0.2s13; CHECK-NEXT: ret14 %as = sext <2 x i16> %a to <2 x i32>15 %bs = sext <2 x i16> %b to <2 x i32>16 %m = mul <2 x i32> %bs, %as17 %sh = ashr <2 x i32> %m, splat (i32 15)18 %ma = tail call <2 x i32> @llvm.smin.v4i32(<2 x i32> %sh, <2 x i32> splat (i32 32767))19 %t = trunc <2 x i32> %ma to <2 x i16>20 ret <2 x i16> %t21}22 23define <4 x i16> @saturating_4xi16(<4 x i16> %a, <4 x i16> %b) {24; CHECK-LABEL: saturating_4xi16:25; CHECK: // %bb.0:26; CHECK-NEXT: sqdmulh v0.4h, v1.4h, v0.4h27; CHECK-NEXT: ret28 %as = sext <4 x i16> %a to <4 x i32>29 %bs = sext <4 x i16> %b to <4 x i32>30 %m = mul <4 x i32> %bs, %as31 %sh = ashr <4 x i32> %m, splat (i32 15)32 %ma = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %sh, <4 x i32> splat (i32 32767))33 %t = trunc <4 x i32> %ma to <4 x i16>34 ret <4 x i16> %t35}36 37define <8 x i16> @saturating_8xi16(<8 x i16> %a, <8 x i16> %b) {38; CHECK-LABEL: saturating_8xi16:39; CHECK: // %bb.0:40; CHECK-NEXT: sqdmulh v0.8h, v1.8h, v0.8h41; CHECK-NEXT: ret42 %as = sext <8 x i16> %a to <8 x i32>43 %bs = sext <8 x i16> %b to <8 x i32>44 %m = mul <8 x i32> %bs, %as45 %sh = ashr <8 x i32> %m, splat (i32 15)46 %ma = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> %sh, <8 x i32> splat (i32 32767))47 %t = trunc <8 x i32> %ma to <8 x i16>48 ret <8 x i16> %t49}50 51define <2 x i32> @saturating_2xi32(<2 x i32> %a, <2 x i32> %b) {52; CHECK-LABEL: saturating_2xi32:53; CHECK: // %bb.0:54; CHECK-NEXT: sqdmulh v0.2s, v1.2s, v0.2s55; CHECK-NEXT: ret56 %as = sext <2 x i32> %a to <2 x i64>57 %bs = sext <2 x i32> %b to <2 x i64>58 %m = mul <2 x i64> %bs, %as59 %sh = ashr <2 x i64> %m, splat (i64 31)60 %ma = tail call <2 x i64> @llvm.smin.v8i64(<2 x i64> %sh, <2 x i64> splat (i64 2147483647))61 %t = trunc <2 x i64> %ma to <2 x i32>62 ret <2 x i32> %t63}64 65define <4 x i32> @saturating_4xi32(<4 x i32> %a, <4 x i32> %b) {66; CHECK-LABEL: saturating_4xi32:67; CHECK: // %bb.0:68; CHECK-NEXT: sqdmulh v0.4s, v1.4s, v0.4s69; CHECK-NEXT: ret70 %as = sext <4 x i32> %a to <4 x i64>71 %bs = sext <4 x i32> %b to <4 x i64>72 %m = mul <4 x i64> %bs, %as73 %sh = ashr <4 x i64> %m, splat (i64 31)74 %ma = tail call <4 x i64> @llvm.smin.v4i64(<4 x i64> %sh, <4 x i64> splat (i64 2147483647))75 %t = trunc <4 x i64> %ma to <4 x i32>76 ret <4 x i32> %t77}78 79define <8 x i32> @saturating_8xi32(<8 x i32> %a, <8 x i32> %b) {80; CHECK-LABEL: saturating_8xi32:81; CHECK: // %bb.0:82; CHECK-NEXT: sqdmulh v1.4s, v3.4s, v1.4s83; CHECK-NEXT: sqdmulh v0.4s, v2.4s, v0.4s84; CHECK-NEXT: ret85 %as = sext <8 x i32> %a to <8 x i64>86 %bs = sext <8 x i32> %b to <8 x i64>87 %m = mul <8 x i64> %bs, %as88 %sh = ashr <8 x i64> %m, splat (i64 31)89 %ma = tail call <8 x i64> @llvm.smin.v8i64(<8 x i64> %sh, <8 x i64> splat (i64 2147483647))90 %t = trunc <8 x i64> %ma to <8 x i32>91 ret <8 x i32> %t92}93 94define <2 x i64> @saturating_2xi32_2xi64(<2 x i32> %a, <2 x i32> %b) {95; CHECK-LABEL: saturating_2xi32_2xi64:96; CHECK: // %bb.0:97; CHECK-NEXT: sqdmulh v0.2s, v1.2s, v0.2s98; CHECK-NEXT: sshll v0.2d, v0.2s, #099; CHECK-NEXT: ret100 %as = sext <2 x i32> %a to <2 x i64>101 %bs = sext <2 x i32> %b to <2 x i64>102 %m = mul <2 x i64> %bs, %as103 %sh = ashr <2 x i64> %m, splat (i64 31)104 %ma = tail call <2 x i64> @llvm.smin.v8i64(<2 x i64> %sh, <2 x i64> splat (i64 2147483647))105 ret <2 x i64> %ma106}107 108define <6 x i16> @saturating_6xi16(<6 x i16> %a, <6 x i16> %b) {109; CHECK-LABEL: saturating_6xi16:110; CHECK: // %bb.0:111; CHECK-NEXT: smull2 v3.4s, v1.8h, v0.8h112; CHECK-NEXT: movi v2.4s, #127, msl #8113; CHECK-NEXT: sqdmulh v0.4h, v1.4h, v0.4h114; CHECK-NEXT: sshr v3.4s, v3.4s, #15115; CHECK-NEXT: smin v2.4s, v3.4s, v2.4s116; CHECK-NEXT: xtn2 v0.8h, v2.4s117; CHECK-NEXT: ret118 %as = sext <6 x i16> %a to <6 x i32>119 %bs = sext <6 x i16> %b to <6 x i32>120 %m = mul <6 x i32> %bs, %as121 %sh = ashr <6 x i32> %m, splat (i32 15)122 %ma = tail call <6 x i32> @llvm.smin.v6i32(<6 x i32> %sh, <6 x i32> splat (i32 32767))123 %t = trunc <6 x i32> %ma to <6 x i16>124 ret <6 x i16> %t125}126 127define <4 x i16> @unsupported_saturation_value_v4i16(<4 x i16> %a, <4 x i16> %b) {128; CHECK-LABEL: unsupported_saturation_value_v4i16:129; CHECK: // %bb.0:130; CHECK-NEXT: smull v0.4s, v1.4h, v0.4h131; CHECK-NEXT: movi v1.4s, #42132; CHECK-NEXT: sshr v0.4s, v0.4s, #15133; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s134; CHECK-NEXT: xtn v0.4h, v0.4s135; CHECK-NEXT: ret136 %as = sext <4 x i16> %a to <4 x i32>137 %bs = sext <4 x i16> %b to <4 x i32>138 %m = mul <4 x i32> %bs, %as139 %sh = ashr <4 x i32> %m, splat (i32 15)140 %ma = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %sh, <4 x i32> splat (i32 42))141 %t = trunc <4 x i32> %ma to <4 x i16>142 ret <4 x i16> %t143}144 145define <4 x i16> @unsupported_shift_value_v4i16(<4 x i16> %a, <4 x i16> %b) {146; CHECK-LABEL: unsupported_shift_value_v4i16:147; CHECK: // %bb.0:148; CHECK-NEXT: smull v0.4s, v1.4h, v0.4h149; CHECK-NEXT: movi v1.4s, #127, msl #8150; CHECK-NEXT: sshr v0.4s, v0.4s, #3151; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s152; CHECK-NEXT: xtn v0.4h, v0.4s153; CHECK-NEXT: ret154 %as = sext <4 x i16> %a to <4 x i32>155 %bs = sext <4 x i16> %b to <4 x i32>156 %m = mul <4 x i32> %bs, %as157 %sh = ashr <4 x i32> %m, splat (i32 3)158 %ma = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %sh, <4 x i32> splat (i32 32767))159 %t = trunc <4 x i32> %ma to <4 x i16>160 ret <4 x i16> %t161}162 163define <2 x i16> @extend_to_illegal_type(<2 x i16> %a, <2 x i16> %b) {164; CHECK-LABEL: extend_to_illegal_type:165; CHECK: // %bb.0:166; CHECK-NEXT: shl v0.2s, v0.2s, #16167; CHECK-NEXT: shl v1.2s, v1.2s, #16168; CHECK-NEXT: sshr v0.2s, v0.2s, #16169; CHECK-NEXT: sshr v1.2s, v1.2s, #16170; CHECK-NEXT: sqdmulh v0.2s, v1.2s, v0.2s171; CHECK-NEXT: ret172 %as = sext <2 x i16> %a to <2 x i48>173 %bs = sext <2 x i16> %b to <2 x i48>174 %m = mul <2 x i48> %bs, %as175 %sh = ashr <2 x i48> %m, splat (i48 15)176 %ma = tail call <2 x i48> @llvm.smin.v4i32(<2 x i48> %sh, <2 x i48> splat (i48 32767))177 %t = trunc <2 x i48> %ma to <2 x i16>178 ret <2 x i16> %t179}180 181define <2 x i11> @illegal_source(<2 x i11> %a, <2 x i11> %b) {182; CHECK-LABEL: illegal_source:183; CHECK: // %bb.0:184; CHECK-NEXT: shl v0.2s, v0.2s, #21185; CHECK-NEXT: shl v1.2s, v1.2s, #21186; CHECK-NEXT: sshr v0.2s, v0.2s, #21187; CHECK-NEXT: sshr v1.2s, v1.2s, #21188; CHECK-NEXT: mul v0.2s, v1.2s, v0.2s189; CHECK-NEXT: movi v1.2s, #127, msl #8190; CHECK-NEXT: sshr v0.2s, v0.2s, #15191; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s192; CHECK-NEXT: ret193 %as = sext <2 x i11> %a to <2 x i32>194 %bs = sext <2 x i11> %b to <2 x i32>195 %m = mul <2 x i32> %bs, %as196 %sh = ashr <2 x i32> %m, splat (i32 15)197 %ma = tail call <2 x i32> @llvm.smin.v2i32(<2 x i32> %sh, <2 x i32> splat (i32 32767))198 %t = trunc <2 x i32> %ma to <2 x i11>199 ret <2 x i11> %t200}201define <1 x i16> @saturating_1xi16(<1 x i16> %a, <1 x i16> %b) {202; CHECK-LABEL: saturating_1xi16:203; CHECK: // %bb.0:204; CHECK-NEXT: zip1 v0.4h, v0.4h, v0.4h205; CHECK-NEXT: zip1 v1.4h, v1.4h, v0.4h206; CHECK-NEXT: shl v0.2s, v0.2s, #16207; CHECK-NEXT: sshr v0.2s, v0.2s, #16208; CHECK-NEXT: shl v1.2s, v1.2s, #16209; CHECK-NEXT: sshr v1.2s, v1.2s, #16210; CHECK-NEXT: mul v0.2s, v1.2s, v0.2s211; CHECK-NEXT: movi v1.2s, #127, msl #8212; CHECK-NEXT: sshr v0.2s, v0.2s, #15213; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s214; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h215; CHECK-NEXT: ret216 %as = sext <1 x i16> %a to <1 x i32>217 %bs = sext <1 x i16> %b to <1 x i32>218 %m = mul <1 x i32> %bs, %as219 %sh = ashr <1 x i32> %m, splat (i32 15)220 %ma = tail call <1 x i32> @llvm.smin.v1i32(<1 x i32> %sh, <1 x i32> splat (i32 32767))221 %t = trunc <1 x i32> %ma to <1 x i16>222 ret <1 x i16> %t223}224