289 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4define void @foo_st2_nxv16i8(<vscale x 16 x i1> %mask, <vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {5; CHECK-LABEL: foo_st2_nxv16i8:6; CHECK: // %bb.0:7; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z18; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z19; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0]10; CHECK-NEXT: ret11 %interleaved.mask = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask)12 %interleaved.value = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2)13 call void @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> %interleaved.mask)14 ret void15}16 17define void @foo_st2_nxv8i16(<vscale x 8 x i1> %mask, <vscale x 8 x i16> %val1, <vscale x 8 x i16> %val2, ptr %p) {18; CHECK-LABEL: foo_st2_nxv8i16:19; CHECK: // %bb.0:20; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z121; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z122; CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0]23; CHECK-NEXT: ret24 %interleaved.mask = call <vscale x 16 x i1> @llvm.vector.interleave2.nxv16i1(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask)25 %interleaved.value = call <vscale x 16 x i16> @llvm.vector.interleave2.nxv16i16(<vscale x 8 x i16> %val1, <vscale x 8 x i16> %val2)26 call void @llvm.masked.store.nxv16i16.p0(<vscale x 16 x i16> %interleaved.value, ptr %p, i32 1, <vscale x 16 x i1> %interleaved.mask)27 ret void28}29 30define void @foo_st2_nxv4i32(<vscale x 4 x i1> %mask, <vscale x 4 x i32> %val1, <vscale x 4 x i32> %val2, ptr %p) {31; CHECK-LABEL: foo_st2_nxv4i32:32; CHECK: // %bb.0:33; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z134; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z135; CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0]36; CHECK-NEXT: ret37 %interleaved.mask = call <vscale x 8 x i1> @llvm.vector.interleave2.nxv8i1(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask)38 %interleaved.value = call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %val1, <vscale x 4 x i32> %val2)39 call void @llvm.masked.store.nxv8i32.p0(<vscale x 8 x i32> %interleaved.value, ptr %p, i32 1, <vscale x 8 x i1> %interleaved.mask)40 ret void41}42 43define void @foo_st2_nxv2i64(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %val1, <vscale x 2 x i64> %val2, ptr %p) {44; CHECK-LABEL: foo_st2_nxv2i64:45; CHECK: // %bb.0:46; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z147; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z148; CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0]49; CHECK-NEXT: ret50 %interleaved.mask = call <vscale x 4 x i1> @llvm.vector.interleave2.nxv4i1(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask)51 %interleaved.value = call <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64> %val1, <vscale x 2 x i64> %val2)52 call void @llvm.masked.store.nxv4i64.p0(<vscale x 4 x i64> %interleaved.value, ptr %p, i32 1, <vscale x 4 x i1> %interleaved.mask)53 ret void54}55 56define void @foo_st4_nxv16i8(<vscale x 16 x i1> %mask, <vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, <vscale x 16 x i8> %val3, <vscale x 16 x i8> %val4, ptr %p) {57; CHECK-LABEL: foo_st4_nxv16i8:58; CHECK: // %bb.0:59; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z360; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z361; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z362; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z363; CHECK-NEXT: st4b { z0.b - z3.b }, p0, [x0]64; CHECK-NEXT: ret65 %interleaved.mask = call <vscale x 64 x i1> @llvm.vector.interleave4.nxv64i1(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask)66 %interleaved.value = call <vscale x 64 x i8> @llvm.vector.interleave4.nxv64i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, <vscale x 16 x i8> %val3, <vscale x 16 x i8> %val4)67 call void @llvm.masked.store.nxv64i8.p0(<vscale x 64 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 64 x i1> %interleaved.mask)68 ret void69}70 71define void @foo_st4_nxv8i16(<vscale x 8 x i1> %mask, <vscale x 8 x i16> %val1, <vscale x 8 x i16> %val2, <vscale x 8 x i16> %val3, <vscale x 8 x i16> %val4, ptr %p) {72; CHECK-LABEL: foo_st4_nxv8i16:73; CHECK: // %bb.0:74; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z375; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z376; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z377; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z378; CHECK-NEXT: st4h { z0.h - z3.h }, p0, [x0]79; CHECK-NEXT: ret80 %interleaved.mask = call <vscale x 32 x i1> @llvm.vector.interleave4.nxv32i1(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask)81 %interleaved.value = call <vscale x 32 x i16> @llvm.vector.interleave4.nxv32i16(<vscale x 8 x i16> %val1, <vscale x 8 x i16> %val2, <vscale x 8 x i16> %val3, <vscale x 8 x i16> %val4)82 call void @llvm.masked.store.nxv32i16.p0(<vscale x 32 x i16> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> %interleaved.mask)83 ret void84}85 86define void @foo_st4_nxv4i32(<vscale x 4 x i1> %mask, <vscale x 4 x i32> %val1, <vscale x 4 x i32> %val2, <vscale x 4 x i32> %val3, <vscale x 4 x i32> %val4, ptr %p) {87; CHECK-LABEL: foo_st4_nxv4i32:88; CHECK: // %bb.0:89; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z390; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z391; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z392; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z393; CHECK-NEXT: st4w { z0.s - z3.s }, p0, [x0]94; CHECK-NEXT: ret95 %interleaved.mask = call <vscale x 16 x i1> @llvm.vector.interleave4.nxv16i1(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask)96 %interleaved.value = call <vscale x 16 x i32> @llvm.vector.interleave4.nxv16i32(<vscale x 4 x i32> %val1, <vscale x 4 x i32> %val2, <vscale x 4 x i32> %val3, <vscale x 4 x i32> %val4)97 call void @llvm.masked.store.nxv16i32.p0(<vscale x 16 x i32> %interleaved.value, ptr %p, i32 1, <vscale x 16 x i1> %interleaved.mask)98 ret void99}100 101define void @foo_st4_nxv2i64(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %val1, <vscale x 2 x i64> %val2, <vscale x 2 x i64> %val3, <vscale x 2 x i64> %val4, ptr %p) {102; CHECK-LABEL: foo_st4_nxv2i64:103; CHECK: // %bb.0:104; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3105; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3106; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3107; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3108; CHECK-NEXT: st4d { z0.d - z3.d }, p0, [x0]109; CHECK-NEXT: ret110 %interleaved.mask = call <vscale x 8 x i1> @llvm.vector.interleave4.nxv4i1(<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask)111 %interleaved.value = call <vscale x 8 x i64> @llvm.vector.interleave4.nxv8i64(<vscale x 2 x i64> %val1, <vscale x 2 x i64> %val2, <vscale x 2 x i64> %val3, <vscale x 2 x i64> %val4)112 call void @llvm.masked.store.nxv8i64.p0(<vscale x 8 x i64> %interleaved.value, ptr %p, i32 1, <vscale x 8 x i1> %interleaved.mask)113 ret void114}115 116define void @foo_st2_nxv16i8_mul_use_mask(<vscale x 16 x i1> %mask, <vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {117; CHECK-LABEL: foo_st2_nxv16i8_mul_use_mask:118; CHECK: // %bb.0:119; CHECK-NEXT: zip1 p1.b, p0.b, p0.b120; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1121; CHECK-NEXT: zip2 p2.b, p0.b, p0.b122; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1123; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0]124; CHECK-NEXT: // fake_use: $p1125; CHECK-NEXT: // fake_use: $p2126; CHECK-NEXT: ret127 %interleaved.mask = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask)128 %interleaved.value = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2)129 call void @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> %interleaved.mask)130 call void (...) @llvm.fake.use(<vscale x 32 x i1> %interleaved.mask)131 ret void132}133 134define void @foo_st2_nxv16i8_mask_of_interleaved_ones(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {135; CHECK-LABEL: foo_st2_nxv16i8_mask_of_interleaved_ones:136; CHECK: // %bb.0:137; CHECK-NEXT: ptrue p0.b138; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1139; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1140; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0]141; CHECK-NEXT: ret142 %interleaved.mask = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> splat(i1 1), <vscale x 16 x i1> splat(i1 1))143 %interleaved.value = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2)144 call void @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> %interleaved.mask)145 ret void146}147 148define void @foo_st2_nxv16i8_all_false_mask(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {149; CHECK-LABEL: foo_st2_nxv16i8_all_false_mask:150; CHECK: // %bb.0:151; CHECK-NEXT: ret152 %interleaved.value = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2)153 call void @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> splat(i1 0))154 ret void155}156 157; DAGCombiner optimises the masked store to a normal store before we even158; reach performMSTORECombine so we never get a chance to convert this to st2b.159define void @foo_st2_nxv16i8_all_true_mask(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {160; CHECK-LABEL: foo_st2_nxv16i8_all_true_mask:161; CHECK: // %bb.0:162; CHECK-NEXT: zip2 z2.b, z0.b, z1.b163; CHECK-NEXT: zip1 z0.b, z0.b, z1.b164; CHECK-NEXT: str z2, [x0, #1, mul vl]165; CHECK-NEXT: str z0, [x0]166; CHECK-NEXT: ret167 %interleaved.value = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2)168 call void @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> splat(i1 1))169 ret void170}171 172 173; Negative tests174 175define void @foo_st2_nxv16i8_mul_use_value(<vscale x 16 x i1> %mask, <vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {176; CHECK-LABEL: foo_st2_nxv16i8_mul_use_value:177; CHECK: // %bb.0:178; CHECK-NEXT: zip2 z2.b, z0.b, z1.b179; CHECK-NEXT: zip1 z0.b, z0.b, z1.b180; CHECK-NEXT: zip2 p1.b, p0.b, p0.b181; CHECK-NEXT: zip1 p0.b, p0.b, p0.b182; CHECK-NEXT: st1b { z2.b }, p1, [x0, #1, mul vl]183; CHECK-NEXT: st1b { z0.b }, p0, [x0]184; CHECK-NEXT: // fake_use: $z0185; CHECK-NEXT: // fake_use: $z2186; CHECK-NEXT: ret187 %interleaved.mask = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask)188 %interleaved.value = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2)189 call void @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> %interleaved.mask)190 call void (...) @llvm.fake.use(<vscale x 32 x i8> %interleaved.value)191 ret void192}193 194; Mask must be an interleave of identical masks.195define void @foo_st2_nxv16i8_bad_mask(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask2, <vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {196; CHECK-LABEL: foo_st2_nxv16i8_bad_mask:197; CHECK: // %bb.0:198; CHECK-NEXT: zip2 z2.b, z0.b, z1.b199; CHECK-NEXT: zip1 z0.b, z0.b, z1.b200; CHECK-NEXT: zip2 p2.b, p0.b, p1.b201; CHECK-NEXT: zip1 p0.b, p0.b, p1.b202; CHECK-NEXT: st1b { z2.b }, p2, [x0, #1, mul vl]203; CHECK-NEXT: st1b { z0.b }, p0, [x0]204; CHECK-NEXT: ret205 %interleaved.mask = call <vscale x 32 x i1> @llvm.vector.interleave2.nxv32i1(<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask2)206 %interleaved.value = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2)207 call void @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> %interleaved.mask)208 ret void209}210 211; Number of parts in mask interleave must match interleave.212define void @foo_st4_nxv4i32_bad_mask2(<vscale x 8 x i1> %mask, <vscale x 4 x i32> %val1, <vscale x 4 x i32> %val2, <vscale x 4 x i32> %val3, <vscale x 4 x i32> %val4, ptr %p) {213; CHECK-LABEL: foo_st4_nxv4i32_bad_mask2:214; CHECK: // %bb.0:215; CHECK-NEXT: zip2 z4.s, z1.s, z3.s216; CHECK-NEXT: zip2 z5.s, z0.s, z2.s217; CHECK-NEXT: zip2 p1.h, p0.h, p0.h218; CHECK-NEXT: zip1 z1.s, z1.s, z3.s219; CHECK-NEXT: zip1 z0.s, z0.s, z2.s220; CHECK-NEXT: zip1 p0.h, p0.h, p0.h221; CHECK-NEXT: punpkhi p2.h, p1.b222; CHECK-NEXT: zip2 z2.s, z5.s, z4.s223; CHECK-NEXT: zip1 z3.s, z5.s, z4.s224; CHECK-NEXT: punpklo p1.h, p1.b225; CHECK-NEXT: zip2 z4.s, z0.s, z1.s226; CHECK-NEXT: zip1 z0.s, z0.s, z1.s227; CHECK-NEXT: st1w { z2.s }, p2, [x0, #3, mul vl]228; CHECK-NEXT: punpkhi p2.h, p0.b229; CHECK-NEXT: punpklo p0.h, p0.b230; CHECK-NEXT: st1w { z3.s }, p1, [x0, #2, mul vl]231; CHECK-NEXT: st1w { z4.s }, p2, [x0, #1, mul vl]232; CHECK-NEXT: st1w { z0.s }, p0, [x0]233; CHECK-NEXT: ret234 %interleaved.mask = call <vscale x 16 x i1> @llvm.vector.interleave2.nxv16i1(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask)235 %interleaved.value = call <vscale x 16 x i32> @llvm.vector.interleave4.nxv16i32(<vscale x 4 x i32> %val1, <vscale x 4 x i32> %val2, <vscale x 4 x i32> %val3, <vscale x 4 x i32> %val4)236 call void @llvm.masked.store.nxv16i32.p0(<vscale x 16 x i32> %interleaved.value, ptr %p, i32 1, <vscale x 16 x i1> %interleaved.mask)237 ret void238}239 240; Mask must come from an interleave or a splat.241define void @foo_st2_nxv16i8_bad_mask3(<vscale x 32 x i1> %mask, <vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {242; CHECK-LABEL: foo_st2_nxv16i8_bad_mask3:243; CHECK: // %bb.0:244; CHECK-NEXT: zip2 z2.b, z0.b, z1.b245; CHECK-NEXT: zip1 z0.b, z0.b, z1.b246; CHECK-NEXT: st1b { z2.b }, p1, [x0, #1, mul vl]247; CHECK-NEXT: st1b { z0.b }, p0, [x0]248; CHECK-NEXT: ret249 %interleaved.value = call <vscale x 32 x i8> @llvm.vector.interleave2.nxv32i8(<vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2)250 call void @llvm.masked.store.nxv32i8.p0(<vscale x 32 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 32 x i1> %mask)251 ret void252}253 254; Each interleaved vector must be exactly 128 bits.255define void @foo_st2_nxv8i8(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %val1, <vscale x 8 x i8> %val2, ptr %p) {256; CHECK-LABEL: foo_st2_nxv8i8:257; CHECK: // %bb.0:258; CHECK-NEXT: zip2 z2.h, z0.h, z1.h259; CHECK-NEXT: zip1 z0.h, z0.h, z1.h260; CHECK-NEXT: zip2 p1.h, p0.h, p0.h261; CHECK-NEXT: zip1 p0.h, p0.h, p0.h262; CHECK-NEXT: uzp1 z0.b, z0.b, z2.b263; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b264; CHECK-NEXT: st1b { z0.b }, p0, [x0]265; CHECK-NEXT: ret266 %interleaved.mask = call <vscale x 16 x i1> @llvm.vector.interleave2.nxv16i1(<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask)267 %interleaved.value = call <vscale x 16 x i8> @llvm.vector.interleave2.nxv16i8(<vscale x 8 x i8> %val1, <vscale x 8 x i8> %val2)268 call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> %interleaved.value, ptr %p, i32 1, <vscale x 16 x i1> %interleaved.mask)269 ret void270}271 272define void @foo_st2_nxv8i8_trunc(<vscale x 4 x i1> %mask, <vscale x 4 x i16> %val1, <vscale x 4 x i16> %val2, ptr %p) {273; CHECK-LABEL: foo_st2_nxv8i8_trunc:274; CHECK: // %bb.0:275; CHECK-NEXT: zip2 z2.s, z0.s, z1.s276; CHECK-NEXT: zip1 z0.s, z0.s, z1.s277; CHECK-NEXT: zip2 p1.s, p0.s, p0.s278; CHECK-NEXT: zip1 p0.s, p0.s, p0.s279; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h280; CHECK-NEXT: uzp1 p0.h, p0.h, p1.h281; CHECK-NEXT: st1b { z0.h }, p0, [x0]282; CHECK-NEXT: ret283 %interleaved.mask = call <vscale x 8 x i1> @llvm.vector.interleave2.nxv8i1(<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask)284 %interleaved.value = call <vscale x 8 x i16> @llvm.vector.interleave2.nxv8i16(<vscale x 4 x i16> %val1, <vscale x 4 x i16> %val2)285 %trunc.value = trunc <vscale x 8 x i16> %interleaved.value to <vscale x 8 x i8>286 call void @llvm.masked.store.nxv8i8.p0(<vscale x 8 x i8> %trunc.value, ptr %p, i32 1, <vscale x 8 x i1> %interleaved.mask)287 ret void288}289