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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple aarch64 -mcpu=tsv110 -mattr=+sve < %s | FileCheck %s3 4; Check that the movprfx intrinsic does not prevent load instructions from5; being scheduled together. As load instructions have long latency, expected6; be preferentially issued.7 8 9; NOTE: The unused paramter ensures z0/z1 is free, avoiding the antidependence for schedule.10define <vscale x 2 x i64> @and_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, ptr %base) {11; CHECK-LABEL: and_i64_zero:12; CHECK: // %bb.0:13; CHECK-NEXT: ld1d { z1.d }, p0/z, [x0]14; CHECK-NEXT: ptrue p1.d15; CHECK-NEXT: movprfx z0, z216; CHECK-NEXT: abs z0.d, p1/m, z2.d17; CHECK-NEXT: add z0.d, z0.d, z1.d18; CHECK-NEXT: ret19 %data0 = tail call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %c, i1 0)20 %data1 = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr %base,21 i32 1,22 <vscale x 2 x i1> %pg,23 <vscale x 2 x i64> undef)24 %out = add <vscale x 2 x i64> %data0, %data125 ret <vscale x 2 x i64> %out26}27 28declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)29declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)30