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1; RUN: llc < %s -mcpu=cortex-a53 -enable-post-misched=false -enable-aa-sched-mi | FileCheck %s2 3; Check that the vector store intrinsic does not prevent fmla instructions from4; being scheduled together. Since the vector loads and stores generated from5; the intrinsics do not alias each other, the store can be pushed past the load.6; This allows fmla instructions to be scheduled together.7 8 9; CHECK: fmla10; CHECK-NEXT: mov11; CHECK-NEXT: mov12; CHECK-NEXT: fmla13; CHECK-NEXT: fmla14; CHECK-NEXT: fmla15target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"16target triple = "aarch64--linux-gnu"17 18%Struct = type { ptr, [9 x double], [16 x {float, float}], [16 x {float, float}], i32, i32 }19 20; Function Attrs: nounwind21define linkonce_odr void @func(ptr nocapture %this, <4 x float> %f) unnamed_addr #0 align 2 {22entry:23 %scevgep = getelementptr %Struct, ptr %this, i64 0, i32 2, i64 8, i32 024 %vec1 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0(ptr %scevgep)25 %ev1 = extractvalue { <4 x float>, <4 x float> } %vec1, 126 %fm1 = fmul contract <4 x float> %f, %ev127 %av1 = fadd contract <4 x float> %f, %fm128 %ev2 = extractvalue { <4 x float>, <4 x float> } %vec1, 029 %fm2 = fmul contract <4 x float> %f, %ev230 %av2 = fadd contract <4 x float> %f, %fm231 %scevgep2 = getelementptr %Struct, ptr %this, i64 0, i32 3, i64 8, i32 032 tail call void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float> %av2, <4 x float> %av1, ptr %scevgep2)33 %scevgep3 = getelementptr %Struct, ptr %this, i64 0, i32 2, i64 12, i32 034 %vec2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0(ptr %scevgep3)35 %ev3 = extractvalue { <4 x float>, <4 x float> } %vec2, 136 %fm3 = fmul contract <4 x float> %f, %ev337 %av3 = fadd contract <4 x float> %f, %fm338 %ev4 = extractvalue { <4 x float>, <4 x float> } %vec2, 039 %fm4 = fmul contract <4 x float> %f, %ev440 %av4 = fadd contract <4 x float> %f, %fm441 %scevgep4 = getelementptr %Struct, ptr %this, i64 0, i32 3, i64 12, i32 042 tail call void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float> %av4, <4 x float> %av3, ptr %scevgep4)43 ret void44}45 46; Function Attrs: nounwind readonly47declare { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0(ptr) #248 49; Function Attrs: nounwind50declare void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float>, <4 x float>, ptr nocapture) #151 52attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "use-soft-float"="false" }53attributes #1 = { nounwind }54attributes #2 = { nounwind readonly }55