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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s3# RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s4# REQUIRES: asserts5 6# Both the accesses should have an offset of 07# CHECK: Num BaseOps: 1, Offset: 0, OffsetIsScalable: 0, Width: LocationSize::precise(4)8# CHECK: Num BaseOps: 1, Offset: 0, OffsetIsScalable: 0, Width: LocationSize::precise(4)9 10--- |11 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"12 target triple = "aarch64"13 14 define ptr @post(ptr %p, i32 %d1, i32 %d2) {15 entry:16 %d3 = mul i32 %d1, %d217 %q = getelementptr i64, ptr %p, i64 318 %r = getelementptr i64, ptr %p, i64 319 store i32 %d3, ptr %p, align 820 %0 = load i32, ptr %r, align 821 store i32 %d1, ptr %p, align 822 %add.ptr = getelementptr inbounds i8, ptr %p, i64 2423 ret ptr %add.ptr24 }25 26...27---28name: post29tracksRegLiveness: true30registers:31 - { id: 0, class: gpr64common, preferred-register: '' }32 - { id: 1, class: gpr32, preferred-register: '' }33 - { id: 2, class: gpr32, preferred-register: '' }34 - { id: 3, class: gpr32, preferred-register: '' }35 - { id: 4, class: gpr64common, preferred-register: '' }36liveins:37 - { reg: '$x0', virtual-reg: '%0' }38 - { reg: '$w1', virtual-reg: '%1' }39 - { reg: '$w2', virtual-reg: '%2' }40body: |41 bb.0.entry:42 liveins: $x0, $w1, $w243 44 ; CHECK-LABEL: name: post45 ; CHECK: liveins: $x0, $w1, $w246 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w248 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w149 ; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY1]], [[COPY]], $wzr50 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x051 ; CHECK-NEXT: STRWui [[MADDWrrr]], [[COPY2]], 0 :: (store (s32) into %ir.p, align 8)52 ; CHECK-NEXT: early-clobber [[COPY2]]:gpr64common = STRWpost [[COPY1]], [[COPY2]], 24 :: (store (s32) into %ir.p, align 8)53 ; CHECK-NEXT: $x0 = COPY [[COPY2]]54 ; CHECK-NEXT: RET_ReallyLR implicit $x055 %2:gpr32 = COPY $w256 %1:gpr32 = COPY $w157 %4:gpr64common = COPY $x058 %3:gpr32 = MADDWrrr %1, %2, $wzr59 STRWui %3, %4, 0 :: (store (s32) into %ir.p, align 8)60 early-clobber %4:gpr64common = STRWpost %1, %4, 24 :: (store (s32) into %ir.p, align 8)61 $x0 = COPY %462 RET_ReallyLR implicit $x063 64...65